From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> The way we calculate the CFB stride/size is kind of a mess, and I'm not sure if we're even allocating enough stolen memory always. Let's make it all more straightforward, and add some new related workarounds as well. Ville Syrjälä (8): drm/i915/fbc: Rewrite the FBC tiling check a bit drm/i915/fbc: Extract intel_fbc_update() drm/i915/fbc: Move the "recompress on activate" to a central place drm/i915/fbc: Polish the skl+ FBC stride override handling drm/i915/fbc: Rework cfb stride/size calculations drm/i915/fbc: Align FBC segments to 512B on glk+ drm/i915/fbc: Implement Wa_16011863758 for icl+ drm/i915/fbc: Allow higher compression limits on FBC1 drivers/gpu/drm/i915/display/intel_display.c | 5 +- drivers/gpu/drm/i915/display/intel_fbc.c | 242 ++++++++++++------- drivers/gpu/drm/i915/display/intel_fbc.h | 2 +- drivers/gpu/drm/i915/i915_drv.h | 6 +- drivers/gpu/drm/i915/i915_reg.h | 9 +- 5 files changed, 168 insertions(+), 96 deletions(-) -- 2.31.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
