> -----Original Message----- > From: Deak, Imre <imre.deak@xxxxxxxxx> > Sent: Monday, June 28, 2021 11:12 PM > To: Gupta, Anshuman <anshuman.gupta@xxxxxxxxx> > Cc: intel-gfx@xxxxxxxxxxxxxxxxxxxxx; Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>; > Kai Vehmanen <kai.vehmanen@xxxxxxxxxxxxxxx>; Shankar, Uma > <uma.shankar@xxxxxxxxx> > Subject: Re: [RFC v3 1/2] drm/i915/dg1: Adjust the AUDIO power domain > > On Tue, Jun 01, 2021 at 03:32:27PM +0530, Anshuman Gupta wrote: > > DG1 and XE_PLD platforms has Audio MMIO/VERBS lies in PG0 power well. > > Adjusting the power domain accordingly to POWER_DOMAIN_AUDIO_VERBS > for > > audio detection and POWER_DOMAIN_AUDIO for audio playback. > > > > Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > Cc: Kai Vehmanen <kai.vehmanen@xxxxxxxxxxxxxxx> > > Cc: Uma Shankar <uma.shankar@xxxxxxxxx> > > Cc: Imre Deak <imre.deak@xxxxxxxxx> > > Signed-off-by: Anshuman Gupta <anshuman.gupta@xxxxxxxxx> > > --- > > .../drm/i915/display/intel_display_power.c | 382 +++++++++++++++++- > > .../drm/i915/display/intel_display_power.h | 1 + > > 2 files changed, 382 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c > > b/drivers/gpu/drm/i915/display/intel_display_power.c > > index 2f7d1664c473..da5894138e8b 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display_power.c > > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c > > @@ -106,6 +106,8 @@ intel_display_power_domain_str(enum > intel_display_power_domain domain) > > return "PORT_OTHER"; > > case POWER_DOMAIN_VGA: > > return "VGA"; > > + case POWER_DOMAIN_AUDIO_VERBS: > > + return "AUDIO_VERBS"; > > Maybe better named AUDIO_MMIO, as VERBS are a subset of that imo. > > > case POWER_DOMAIN_AUDIO: > > return "AUDIO"; > > Let's also rename this to AUDIO_PLAYBACK for clarity. > > > case POWER_DOMAIN_AUX_A: > > @@ -2499,6 +2501,7 @@ intel_display_power_put_mask_in_set(struct > drm_i915_private *i915, > > BIT_ULL(POWER_DOMAIN_PORT_DSI) | \ > > BIT_ULL(POWER_DOMAIN_PORT_CRT) | \ > > BIT_ULL(POWER_DOMAIN_VGA) | \ > > + BIT_ULL(POWER_DOMAIN_AUDIO_VERBS) | \ > > BIT_ULL(POWER_DOMAIN_AUDIO) | \ > > BIT_ULL(POWER_DOMAIN_AUX_B) | \ > > BIT_ULL(POWER_DOMAIN_AUX_C) | \ > > @@ -2549,6 +2552,7 @@ intel_display_power_put_mask_in_set(struct > drm_i915_private *i915, > > BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \ > > BIT_ULL(POWER_DOMAIN_PORT_DSI) | \ > > BIT_ULL(POWER_DOMAIN_VGA) | \ > > + BIT_ULL(POWER_DOMAIN_AUDIO_VERBS) | \ > > BIT_ULL(POWER_DOMAIN_AUDIO) | \ > > BIT_ULL(POWER_DOMAIN_AUX_B) | \ > > BIT_ULL(POWER_DOMAIN_AUX_C) | \ > > @@ -2582,6 +2586,7 @@ intel_display_power_put_mask_in_set(struct > drm_i915_private *i915, > > BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \ > > BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \ > > BIT_ULL(POWER_DOMAIN_VGA) | \ > > + BIT_ULL(POWER_DOMAIN_AUDIO_VERBS) | \ > > BIT_ULL(POWER_DOMAIN_AUDIO) | \ > > BIT_ULL(POWER_DOMAIN_INIT)) > > > > @@ -2598,6 +2603,7 @@ intel_display_power_put_mask_in_set(struct > drm_i915_private *i915, > > BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \ > > BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \ > > BIT_ULL(POWER_DOMAIN_VGA) | \ > > + BIT_ULL(POWER_DOMAIN_AUDIO_VERBS) | \ > > BIT_ULL(POWER_DOMAIN_AUDIO) | \ > > BIT_ULL(POWER_DOMAIN_INIT)) > > > > @@ -2616,6 +2622,7 @@ intel_display_power_put_mask_in_set(struct > drm_i915_private *i915, > > BIT_ULL(POWER_DOMAIN_AUX_B) | \ > > BIT_ULL(POWER_DOMAIN_AUX_C) | \ > > BIT_ULL(POWER_DOMAIN_AUX_D) | \ > > + BIT_ULL(POWER_DOMAIN_AUDIO_VERBS) | \ > > BIT_ULL(POWER_DOMAIN_AUDIO) | \ > > BIT_ULL(POWER_DOMAIN_VGA) | \ > > BIT_ULL(POWER_DOMAIN_INIT)) > > @@ -2651,6 +2658,7 @@ intel_display_power_put_mask_in_set(struct > drm_i915_private *i915, > > BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ > > BIT_ULL(POWER_DOMAIN_AUX_B) | \ > > BIT_ULL(POWER_DOMAIN_AUX_C) | \ > > + BIT_ULL(POWER_DOMAIN_AUDIO_VERBS) | \ > > BIT_ULL(POWER_DOMAIN_AUDIO) | \ > > BIT_ULL(POWER_DOMAIN_VGA) | \ > > BIT_ULL(POWER_DOMAIN_INIT)) > > @@ -2684,6 +2692,7 @@ intel_display_power_put_mask_in_set(struct > drm_i915_private *i915, > > BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ > > BIT_ULL(POWER_DOMAIN_AUX_B) | \ > > BIT_ULL(POWER_DOMAIN_AUX_C) | \ > > + BIT_ULL(POWER_DOMAIN_AUDIO_VERBS) | \ > > BIT_ULL(POWER_DOMAIN_AUDIO) | \ > > BIT_ULL(POWER_DOMAIN_VGA) | \ > > BIT_ULL(POWER_DOMAIN_INIT)) > > @@ -2739,6 +2748,7 @@ intel_display_power_put_mask_in_set(struct > drm_i915_private *i915, > > BIT_ULL(POWER_DOMAIN_AUX_C) | \ > > BIT_ULL(POWER_DOMAIN_AUX_D) | \ > > BIT_ULL(POWER_DOMAIN_AUX_F) | \ > > + BIT_ULL(POWER_DOMAIN_AUDIO_VERBS) | \ > > BIT_ULL(POWER_DOMAIN_AUDIO) | \ > > BIT_ULL(POWER_DOMAIN_VGA) | \ > > BIT_ULL(POWER_DOMAIN_INIT)) > > @@ -2821,6 +2831,7 @@ intel_display_power_put_mask_in_set(struct > drm_i915_private *i915, > > BIT_ULL(POWER_DOMAIN_AUX_E_TBT) | \ > > BIT_ULL(POWER_DOMAIN_AUX_F_TBT) | \ > > BIT_ULL(POWER_DOMAIN_VGA) | \ > > + BIT_ULL(POWER_DOMAIN_AUDIO_VERBS) | \ > > BIT_ULL(POWER_DOMAIN_AUDIO) | \ > > BIT_ULL(POWER_DOMAIN_INIT)) > > /* > > @@ -2913,6 +2924,7 @@ intel_display_power_put_mask_in_set(struct > drm_i915_private *i915, > > BIT_ULL(POWER_DOMAIN_AUX_TBT5) | \ > > BIT_ULL(POWER_DOMAIN_AUX_TBT6) | \ > > BIT_ULL(POWER_DOMAIN_VGA) | \ > > + BIT_ULL(POWER_DOMAIN_AUDIO_VERBS) | \ > > BIT_ULL(POWER_DOMAIN_AUDIO) | \ > > BIT_ULL(POWER_DOMAIN_INIT)) > > > > @@ -2983,6 +2995,7 @@ intel_display_power_put_mask_in_set(struct > drm_i915_private *i915, > > RKL_PW_4_POWER_DOMAINS | \ > > BIT_ULL(POWER_DOMAIN_PIPE_B) | \ > > BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ > > + BIT_ULL(POWER_DOMAIN_AUDIO_VERBS) | \ > > BIT_ULL(POWER_DOMAIN_AUDIO) | \ > > BIT_ULL(POWER_DOMAIN_VGA) | \ > > BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ > > @@ -3020,6 +3033,42 @@ intel_display_power_put_mask_in_set(struct > drm_i915_private *i915, > > BIT_ULL(POWER_DOMAIN_AUX_B) | \ > > BIT_ULL(POWER_DOMAIN_INIT)) > > > > +/* > > + * DG1 Audio MMIO/VERBS lies in PG0 power well. > > + */ > > + > > +#define DG1_PW_2_POWER_DOMAINS ( \ > > + DG1_PW_3_POWER_DOMAINS | \ > > + BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) | \ > > + BIT_ULL(POWER_DOMAIN_INIT)) > > Let's keep the order for other platforms and move DG1_PW_2 after the > DG1_PW_3 definition. > > > + > > +#define DG1_PW_3_POWER_DOMAINS ( \ > > + TGL_PW_4_POWER_DOMAINS | \ > > + BIT_ULL(POWER_DOMAIN_PIPE_B) | \ > > + BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ > > + BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ > > + BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) | \ > > + BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC2) | \ > > + BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC3) | \ > > + BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC4) | \ > > + BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC5) | \ > > + BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC6) | \ > > DG1 has only TC1/2 DDIs. > > > + BIT_ULL(POWER_DOMAIN_AUX_USBC1) | \ > > + BIT_ULL(POWER_DOMAIN_AUX_USBC2) | \ > > + BIT_ULL(POWER_DOMAIN_AUX_USBC3) | \ > > + BIT_ULL(POWER_DOMAIN_AUX_USBC4) | \ > > + BIT_ULL(POWER_DOMAIN_AUX_USBC5) | \ > > + BIT_ULL(POWER_DOMAIN_AUX_USBC6) | \ > > Only AUX_USBC1/2. > > > + BIT_ULL(POWER_DOMAIN_AUX_TBT1) | \ > > + BIT_ULL(POWER_DOMAIN_AUX_TBT2) | \ > > + BIT_ULL(POWER_DOMAIN_AUX_TBT3) | \ > > + BIT_ULL(POWER_DOMAIN_AUX_TBT4) | \ > > + BIT_ULL(POWER_DOMAIN_AUX_TBT5) | \ > > + BIT_ULL(POWER_DOMAIN_AUX_TBT6) | \ > > No TBT on DG1. > > > + BIT_ULL(POWER_DOMAIN_VGA) | \ > > + BIT_ULL(POWER_DOMAIN_AUDIO) | \ > > + BIT_ULL(POWER_DOMAIN_INIT)) > > + > > > What about DC3co? I read about this change on HSD 1407435623: > "DC3 clock off mode is not possible with this mode since cdclk cannot be turned > off." > > Will DMC take care of this? > > Could you please open a ticket to clarify the "Audio codec idle and disabled." > DC3co requirement text wrt. this change on the BSpec/49196 page? Thanks Imre for Review, have raised a ticket for above issue https://gfxspecs.intel.com/Predator/Issue/27828 I will fix all the review comments in next revision. Br, Anshuman Gupta. > > > /* > > * XE_LPD Power Domains > > * > > What about the D13 platform? Looks like it has the same split between the > MMIO and playback audio functionality. > > > > @@ -4497,6 +4546,335 @@ static const struct i915_power_well_desc > tgl_power_wells[] = { > > }, > > }; > > > > +static const struct i915_power_well_desc dg1_power_wells[] = { > > Let's follow the order of platform definitions and move this after the rkl power > well list. > > > + { > > + .name = "always-on", > > + .always_on = true, > > + .domains = POWER_DOMAIN_MASK, > > + .ops = &i9xx_always_on_power_well_ops, > > + .id = DISP_PW_ID_NONE, > > + }, > > + { > > + .name = "power well 1", > > + /* Handled by the DMC firmware */ > > + .always_on = true, > > + .domains = 0, > > + .ops = &hsw_power_well_ops, > > + .id = SKL_DISP_PW_1, > > + { > > + .hsw.regs = &hsw_power_well_regs, > > + .hsw.idx = ICL_PW_CTL_IDX_PW_1, > > + .hsw.has_fuses = true, > > + }, > > + }, > > + { > > + .name = "DC off", > > + .domains = TGL_DISPLAY_DC_OFF_POWER_DOMAINS, > > + .ops = &gen9_dc_off_power_well_ops, > > + .id = SKL_DISP_DC_OFF, > > + }, > > + { > > + .name = "power well 2", > > + .domains = DG1_PW_2_POWER_DOMAINS, > > + .ops = &hsw_power_well_ops, > > + .id = SKL_DISP_PW_2, > > + { > > + .hsw.regs = &hsw_power_well_regs, > > + .hsw.idx = ICL_PW_CTL_IDX_PW_2, > > + .hsw.has_fuses = true, > > + }, > > + }, > > + { > > + .name = "power well 3", > > + .domains = DG1_PW_3_POWER_DOMAINS, > > + .ops = &hsw_power_well_ops, > > + .id = ICL_DISP_PW_3, > > + { > > + .hsw.regs = &hsw_power_well_regs, > > + .hsw.idx = ICL_PW_CTL_IDX_PW_3, > > + .hsw.irq_pipe_mask = BIT(PIPE_B), > > + .hsw.has_vga = true, > > + .hsw.has_fuses = true, > > + }, > > + }, > > + { > > + .name = "DDI A IO", > > + .domains = ICL_DDI_IO_A_POWER_DOMAINS, > > + .ops = &hsw_power_well_ops, > > + .id = DISP_PW_ID_NONE, > > + { > > + .hsw.regs = &icl_ddi_power_well_regs, > > + .hsw.idx = ICL_PW_CTL_IDX_DDI_A, > > + } > > + }, > > + { > > + .name = "DDI B IO", > > + .domains = ICL_DDI_IO_B_POWER_DOMAINS, > > + .ops = &hsw_power_well_ops, > > + .id = DISP_PW_ID_NONE, > > + { > > + .hsw.regs = &icl_ddi_power_well_regs, > > + .hsw.idx = ICL_PW_CTL_IDX_DDI_B, > > + } > > + }, > > + { > > + .name = "DDI C IO", > > + .domains = ICL_DDI_IO_C_POWER_DOMAINS, > > + .ops = &hsw_power_well_ops, > > + .id = DISP_PW_ID_NONE, > > + { > > + .hsw.regs = &icl_ddi_power_well_regs, > > + .hsw.idx = ICL_PW_CTL_IDX_DDI_C, > > + } > > + }, > > No DDI C on DG1. > > > + { > > + .name = "DDI IO TC1", > > + .domains = TGL_DDI_IO_TC1_POWER_DOMAINS, > > + .ops = &hsw_power_well_ops, > > + .id = DISP_PW_ID_NONE, > > + { > > + .hsw.regs = &icl_ddi_power_well_regs, > > + .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1, > > + }, > > + }, > > + { > > + .name = "DDI IO TC2", > > + .domains = TGL_DDI_IO_TC2_POWER_DOMAINS, > > + .ops = &hsw_power_well_ops, > > + .id = DISP_PW_ID_NONE, > > + { > > + .hsw.regs = &icl_ddi_power_well_regs, > > + .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2, > > + }, > > + }, > > + { > > + .name = "DDI IO TC3", > > + .domains = TGL_DDI_IO_TC3_POWER_DOMAINS, > > + .ops = &hsw_power_well_ops, > > + .id = DISP_PW_ID_NONE, > > + { > > + .hsw.regs = &icl_ddi_power_well_regs, > > + .hsw.idx = TGL_PW_CTL_IDX_DDI_TC3, > > + }, > > + }, > > + { > > + .name = "DDI IO TC4", > > + .domains = TGL_DDI_IO_TC4_POWER_DOMAINS, > > + .ops = &hsw_power_well_ops, > > + .id = DISP_PW_ID_NONE, > > + { > > + .hsw.regs = &icl_ddi_power_well_regs, > > + .hsw.idx = TGL_PW_CTL_IDX_DDI_TC4, > > + }, > > + }, > > + { > > + .name = "DDI IO TC5", > > + .domains = TGL_DDI_IO_TC5_POWER_DOMAINS, > > + .ops = &hsw_power_well_ops, > > + .id = DISP_PW_ID_NONE, > > + { > > + .hsw.regs = &icl_ddi_power_well_regs, > > + .hsw.idx = TGL_PW_CTL_IDX_DDI_TC5, > > + }, > > + }, > > + { > > + .name = "DDI IO TC6", > > + .domains = TGL_DDI_IO_TC6_POWER_DOMAINS, > > + .ops = &hsw_power_well_ops, > > + .id = DISP_PW_ID_NONE, > > + { > > + .hsw.regs = &icl_ddi_power_well_regs, > > + .hsw.idx = TGL_PW_CTL_IDX_DDI_TC6, > > + }, > > + }, > > Only DDI TC1/2 on DG1. > > > + { > > + .name = "AUX A", > > + .domains = TGL_AUX_A_IO_POWER_DOMAINS, > > + .ops = &icl_aux_power_well_ops, > > + .id = DISP_PW_ID_NONE, > > + { > > + .hsw.regs = &icl_aux_power_well_regs, > > + .hsw.idx = ICL_PW_CTL_IDX_AUX_A, > > + }, > > + }, > > + { > > + .name = "AUX B", > > + .domains = TGL_AUX_B_IO_POWER_DOMAINS, > > + .ops = &icl_aux_power_well_ops, > > + .id = DISP_PW_ID_NONE, > > + { > > + .hsw.regs = &icl_aux_power_well_regs, > > + .hsw.idx = ICL_PW_CTL_IDX_AUX_B, > > + }, > > + }, > > + { > > + .name = "AUX C", > > + .domains = TGL_AUX_C_IO_POWER_DOMAINS, > > + .ops = &icl_aux_power_well_ops, > > + .id = DISP_PW_ID_NONE, > > + { > > + .hsw.regs = &icl_aux_power_well_regs, > > + .hsw.idx = ICL_PW_CTL_IDX_AUX_C, > > + }, > > + }, > > No AUX C on DG1. > > > + { > > + .name = "AUX USBC1", > > + .domains = TGL_AUX_IO_USBC1_POWER_DOMAINS, > > + .ops = &icl_aux_power_well_ops, > > + .id = DISP_PW_ID_NONE, > > + { > > + .hsw.regs = &icl_aux_power_well_regs, > > + .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1, > > + .hsw.is_tc_tbt = false, > > + }, > > + }, > > + { > > + .name = "AUX USBC2", > > + .domains = TGL_AUX_IO_USBC2_POWER_DOMAINS, > > + .ops = &icl_aux_power_well_ops, > > + .id = DISP_PW_ID_NONE, > > + { > > + .hsw.regs = &icl_aux_power_well_regs, > > + .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2, > > + .hsw.is_tc_tbt = false, > > + }, > > + }, > > + { > > + .name = "AUX USBC3", > > + .domains = TGL_AUX_IO_USBC3_POWER_DOMAINS, > > + .ops = &icl_aux_power_well_ops, > > + .id = DISP_PW_ID_NONE, > > + { > > + .hsw.regs = &icl_aux_power_well_regs, > > + .hsw.idx = TGL_PW_CTL_IDX_AUX_TC3, > > + .hsw.is_tc_tbt = false, > > + }, > > + }, > > + { > > + .name = "AUX USBC4", > > + .domains = TGL_AUX_IO_USBC4_POWER_DOMAINS, > > + .ops = &icl_aux_power_well_ops, > > + .id = DISP_PW_ID_NONE, > > + { > > + .hsw.regs = &icl_aux_power_well_regs, > > + .hsw.idx = TGL_PW_CTL_IDX_AUX_TC4, > > + .hsw.is_tc_tbt = false, > > + }, > > + }, > > + { > > + .name = "AUX USBC5", > > + .domains = TGL_AUX_IO_USBC5_POWER_DOMAINS, > > + .ops = &icl_aux_power_well_ops, > > + .id = DISP_PW_ID_NONE, > > + { > > + .hsw.regs = &icl_aux_power_well_regs, > > + .hsw.idx = TGL_PW_CTL_IDX_AUX_TC5, > > + .hsw.is_tc_tbt = false, > > + }, > > + }, > > + { > > + .name = "AUX USBC6", > > + .domains = TGL_AUX_IO_USBC6_POWER_DOMAINS, > > + .ops = &icl_aux_power_well_ops, > > + .id = DISP_PW_ID_NONE, > > + { > > + .hsw.regs = &icl_aux_power_well_regs, > > + .hsw.idx = TGL_PW_CTL_IDX_AUX_TC6, > > + .hsw.is_tc_tbt = false, > > + }, > > + }, > > Only AUX USBC1/2 on DG1. > > > + { > > + .name = "AUX TBT1", > > + .domains = TGL_AUX_IO_TBT1_POWER_DOMAINS, > > + .ops = &icl_aux_power_well_ops, > > + .id = DISP_PW_ID_NONE, > > + { > > + .hsw.regs = &icl_aux_power_well_regs, > > + .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1, > > + .hsw.is_tc_tbt = true, > > + }, > > + }, > > + { > > + .name = "AUX TBT2", > > + .domains = TGL_AUX_IO_TBT2_POWER_DOMAINS, > > + .ops = &icl_aux_power_well_ops, > > + .id = DISP_PW_ID_NONE, > > + { > > + .hsw.regs = &icl_aux_power_well_regs, > > + .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT2, > > + .hsw.is_tc_tbt = true, > > + }, > > + }, > > + { > > + .name = "AUX TBT3", > > + .domains = TGL_AUX_IO_TBT3_POWER_DOMAINS, > > + .ops = &icl_aux_power_well_ops, > > + .id = DISP_PW_ID_NONE, > > + { > > + .hsw.regs = &icl_aux_power_well_regs, > > + .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT3, > > + .hsw.is_tc_tbt = true, > > + }, > > + }, > > + { > > + .name = "AUX TBT4", > > + .domains = TGL_AUX_IO_TBT4_POWER_DOMAINS, > > + .ops = &icl_aux_power_well_ops, > > + .id = DISP_PW_ID_NONE, > > + { > > + .hsw.regs = &icl_aux_power_well_regs, > > + .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT4, > > + .hsw.is_tc_tbt = true, > > + }, > > + }, > > + { > > + .name = "AUX TBT5", > > + .domains = TGL_AUX_IO_TBT5_POWER_DOMAINS, > > + .ops = &icl_aux_power_well_ops, > > + .id = DISP_PW_ID_NONE, > > + { > > + .hsw.regs = &icl_aux_power_well_regs, > > + .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT5, > > + .hsw.is_tc_tbt = true, > > + }, > > + }, > > + { > > + .name = "AUX TBT6", > > + .domains = TGL_AUX_IO_TBT6_POWER_DOMAINS, > > + .ops = &icl_aux_power_well_ops, > > + .id = DISP_PW_ID_NONE, > > + { > > + .hsw.regs = &icl_aux_power_well_regs, > > + .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT6, > > + .hsw.is_tc_tbt = true, > > + }, > > + }, > > No TBT on DG1. > > > + { > > + .name = "power well 4", > > + .domains = TGL_PW_4_POWER_DOMAINS, > > + .ops = &hsw_power_well_ops, > > + .id = DISP_PW_ID_NONE, > > + { > > + .hsw.regs = &hsw_power_well_regs, > > + .hsw.idx = ICL_PW_CTL_IDX_PW_4, > > + .hsw.has_fuses = true, > > + .hsw.irq_pipe_mask = BIT(PIPE_C), > > + } > > + }, > > + { > > + .name = "power well 5", > > + .domains = TGL_PW_5_POWER_DOMAINS, > > + .ops = &hsw_power_well_ops, > > + .id = DISP_PW_ID_NONE, > > + { > > + .hsw.regs = &hsw_power_well_regs, > > + .hsw.idx = TGL_PW_CTL_IDX_PW_5, > > + .hsw.has_fuses = true, > > + .hsw.irq_pipe_mask = BIT(PIPE_D), > > + }, > > + }, > > +}; > > + > > static const struct i915_power_well_desc rkl_power_wells[] = { > > { > > .name = "always-on", > > @@ -5110,9 +5488,11 @@ int intel_power_domains_init(struct > drm_i915_private *dev_priv) > > err = 0; > > } else if (DISPLAY_VER(dev_priv) >= 13) { > > err = set_power_wells(power_domains, xelpd_power_wells); > > - } else if (IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv)) { > > + } else if (IS_ALDERLAKE_S(dev_priv)) { > > err = set_power_wells_mask(power_domains, tgl_power_wells, > > > BIT_ULL(TGL_DISP_PW_TC_COLD_OFF)); > > + } else if (IS_DG1(dev_priv)) { > > + err = set_power_wells(power_domains, dg1_power_wells); > > Let's move this after the D13 case. > > > } else if (IS_ROCKETLAKE(dev_priv)) { > > err = set_power_wells(power_domains, rkl_power_wells); > > } else if (DISPLAY_VER(dev_priv) == 12) { diff --git > > a/drivers/gpu/drm/i915/display/intel_display_power.h > > b/drivers/gpu/drm/i915/display/intel_display_power.h > > index 4f0917df4375..d9c824264ac9 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display_power.h > > +++ b/drivers/gpu/drm/i915/display/intel_display_power.h > > @@ -76,6 +76,7 @@ enum intel_display_power_domain { > > POWER_DOMAIN_PORT_CRT, > > POWER_DOMAIN_PORT_OTHER, > > POWER_DOMAIN_VGA, > > + POWER_DOMAIN_AUDIO_VERBS, > > POWER_DOMAIN_AUDIO, > > POWER_DOMAIN_AUX_A, > > POWER_DOMAIN_AUX_B, > > -- > > 2.26.2 > > _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
