> -----Original Message-----
> From: Souza, Jose <jose.souza@xxxxxxxxx>
> Sent: Thursday, June 17, 2021 2:18 PM
> To: Mun, Gwan-gyeong <gwan-gyeong.mun@xxxxxxxxx>; Srivatsa, Anusha
> <anusha.srivatsa@xxxxxxxxx>; intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> Subject: Re: [PATCH 1/5] drm/i915/display: Limit disabling PSR
> around cdclk changes to ADL-P
>
> On Thu, 2021-06-17 at 14:12 -0700, Anusha Srivatsa wrote:
> > From: Gwan-gyeong Mun <gwan-gyeong.mun@xxxxxxxxx>
> >
> > Only ADL-P platform requires a temporal disabling of PSR for changing
> > the CDCLK PLL frequency with crawling. Changing the CDCLK PLL
> > frequency on prior platforms of ADL-P or changing the CDCLK PLL
> > frequency without crawling on ADL-P don't need to disable of PSR.
>
> This is only hiding a possible bug found in ICL under the IS_ALDERLAKE_P()
> check.
> There is no reason to not pause PSR in older platforms during cdclck changes.
According to 15729, pausing PSR during cdclk changes is not valid.
Anusha
> >
> > Bspec: 49207
> >
> > Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> > Cc: Mika Kahola <mika.kahola@xxxxxxxxx>
> > Cc: Stanislav Lisovskiy <stanislav.lisovskiy@xxxxxxxxx>
> > Cc: Anusha Srivatsa <anusha.srivatsa@xxxxxxxxx>
> > Fixes: 17c1a4b7ac6f ("drm/i915: Disable PSR around cdclk change")
> > Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@xxxxxxxxx>
> > ---
> > drivers/gpu/drm/i915/display/intel_cdclk.c | 22
> > ++++++++++++++++------
> > 1 file changed, 16 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > index 613ffcc68eba..6da426d26aac 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > @@ -1962,10 +1962,18 @@ static void intel_set_cdclk(struct
> > drm_i915_private *dev_priv,
> >
> > intel_dump_cdclk_config(cdclk_config, "Changing CDCLK to");
> >
> > - for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
> > - struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > + /*
> > + * Only ADL-P platform requires a temporal disabling of PSR for
> changing
> > + * the CDCLK PLL frequency with crawling.
> > + * Changing the CDCLK PLL frequency on prior platforms of ADL-P or
> changing
> > + * the CDCLK PLL frequency without crawling on ADL-P don't need to
> disable of PSR.
> > + */
> > + if (IS_ALDERLAKE_P(dev_priv)) {
> > + for_each_intel_encoder_with_psr(&dev_priv->drm,
> encoder) {
> > + struct intel_dp *intel_dp =
> enc_to_intel_dp(encoder);
> >
> > - intel_psr_pause(intel_dp);
> > + intel_psr_pause(intel_dp);
> > + }
> > }
> >
> > /*
> > @@ -1990,10 +1998,12 @@ static void intel_set_cdclk(struct
> drm_i915_private *dev_priv,
> > }
> > mutex_unlock(&dev_priv->gmbus_mutex);
> >
> > - for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
> > - struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > + if (IS_ALDERLAKE_P(dev_priv)) {
> > + for_each_intel_encoder_with_psr(&dev_priv->drm,
> encoder) {
> > + struct intel_dp *intel_dp =
> enc_to_intel_dp(encoder);
> >
> > - intel_psr_resume(intel_dp);
> > + intel_psr_resume(intel_dp);
> > + }
> > }
> >
> > if (drm_WARN(&dev_priv->drm,
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