When determining the slice/subslice to use for steering multicast register reads we need to not only consider the fusing (to avoid steering to a fused off instance), but also the "minconfig" that the hardware uses to wake from RC6 when render power gating is enabled on some platforms. Although it isn't well-documented, certain platforms (e.g., EHL/JSL) will initially only power up a single instance of multicast registers when forcewake is grabbed if the GPU isn't actually busy. In these cases, only the minconfig slice/subslice will return valid, non-zero reads so we need to ensure that we steer to the minconfig specifically. The minconfig should always be the lowest slice/subslice that isn't fused off; as such, we should pick our steering target with ffs() instead of fls() during initialization. This steering change is especially important on EHL/JSL since there are cases where the hardware appears to not honor the driver's attempts to disable render powergating via the POWERGATE_ENABLE (0xA210) register and will continue to only wake the minconfig's slice/subslice in response to forcewake. We can see this in certain reset or suspend/resume cases where i915 tries to disable render powergating and then re-applies workarounds before re-enabling powergating; the workarounds apply successfully, but the readback verification will fail if we aren't steering to the minconfig register instance. References: https://gitlab.freedesktop.org/drm/intel/-/issues/1222 Cc: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@xxxxxxxxx> Signed-off-by: Matt Roper <matthew.d.roper@xxxxxxxxx> --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index b62d1e31a645..0c973678bf03 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -991,13 +991,13 @@ wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal) l3_en = ~0; } - slice = fls(sseu->slice_mask) - 1; - subslice = fls(l3_en & intel_sseu_get_subslices(sseu, slice)); + slice = ffs(sseu->slice_mask) - 1; + subslice = ffs(l3_en & intel_sseu_get_subslices(sseu, slice)); if (!subslice) { drm_warn(&i915->drm, "No common index found between subslice mask %x and L3 bank mask %x!\n", intel_sseu_get_subslices(sseu, slice), l3_en); - subslice = fls(l3_en); + subslice = ffs(l3_en); drm_WARN_ON(&i915->drm, !subslice); } subslice--; -- 2.25.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
