> -----Original Message-----
> From: Mun, Gwan-gyeong <gwan-gyeong.mun@xxxxxxxxx>
> Sent: Tuesday, June 1, 2021 3:48 PM
> To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> Cc: Souza, Jose <jose.souza@xxxxxxxxx>; Lisovskiy, Stanislav
> <stanislav.lisovskiy@xxxxxxxxx>; ville.syrjala@xxxxxxxxxxxxxxx; Roper,
> Matthew D <matthew.d.roper@xxxxxxxxx>; Kahola, Mika
> <mika.kahola@xxxxxxxxx>
> Subject: [PATCH v2 2/2] drm/i915: Disable PSR around cdclk changes
>
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> AUX logic is often clocked from cdclk. Disable PSR to make sure there are no
> hw initiated AUX transactions in flight while we change the cdclk frequency.
>
> Cc: Mika Kahola <mika.kahola@xxxxxxxxx>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@xxxxxxxxx>
Reviewed-by: Mika Kahola <mika.kahola@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 4656a6edc3be..618a9e1e2b0c 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -28,6 +28,7 @@
> #include "intel_cdclk.h"
> #include "intel_de.h"
> #include "intel_display_types.h"
> +#include "intel_psr.h"
> #include "intel_sideband.h"
>
> /**
> @@ -1908,6 +1909,12 @@ static void intel_set_cdclk(struct
> drm_i915_private *dev_priv,
>
> intel_dump_cdclk_config(cdclk_config, "Changing CDCLK to");
>
> + for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
> + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +
> + intel_psr_pause(intel_dp);
> + }
> +
> /*
> * Lock aux/gmbus while we change cdclk in case those
> * functions use cdclk. Not all platforms/ports do, @@ -1930,6
> +1937,12 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv,
> }
> mutex_unlock(&dev_priv->gmbus_mutex);
>
> + for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
> + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +
> + intel_psr_resume(intel_dp);
> + }
> +
> if (drm_WARN(&dev_priv->drm,
> intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config),
> "cdclk state doesn't match!\n")) {
> --
> 2.31.1
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