Hi 2013/4/11 Daniel Vetter <daniel.vetter at ffwll.ch>: > Just blows through 50ms for naught, since the pipe is off. > > Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch> Looks correct, but can you also please add some WARNs in case the pipe is actually on? Check haswell_crtc_mode_set for examples: - WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) & (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE)); - WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE); > --- > drivers/gpu/drm/i915/intel_display.c | 4 ---- > 1 file changed, 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 4f9f846..e91e01c 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -4632,8 +4632,6 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc, > > i9xx_set_pipeconf(intel_crtc); > > - intel_wait_for_vblank(dev, pipe); > - > I915_WRITE(DSPCNTR(plane), dspcntr); > POSTING_READ(DSPCNTR(plane)); > > @@ -5605,8 +5603,6 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc, > > ironlake_set_pipeconf(crtc, adjusted_mode, dither); > > - intel_wait_for_vblank(dev, pipe); > - > /* Set up the display plane register */ > I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE); > POSTING_READ(DSPCNTR(plane)); > -- > 1.7.10.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Paulo Zanoni
