On Mon, 24 May 2021, Dave Airlie <airlied@xxxxxxxxx> wrote:
> Can someone land this in drm-intel-next asap? it's breaking drm-tip development.
Pushed, sorry for the hiccup. Need to get CONFIG_DRM_I915_GVT=y enabled
in CI.
BR,
Jani.
>
> Dave.
>
> On Sat, 22 May 2021 at 16:44, Lucas De Marchi <lucas.demarchi@xxxxxxxxx> wrote:
>>
>> On Fri, May 21, 2021 at 10:40:47AM -0700, Anusha Srivatsa wrote:
>> >Propogate changes to macros name containing CSR_*
>> >to DMC_* from display side.
>> >
>> >Fixes: 0633cdcbaa77 ("drm/i915/dmc: Rename macro names containing csr")
>> >Cc: intel-gvt-dev@xxxxxxxxxxxxxxxxxxxxx
>> >Cc: Jani Nikula <jani.nikula@xxxxxxxxxxxxxxx>
>> >Cc: Lucas De Marchi <lucas.demarchi@xxxxxxxxx>
>> >Signed-off-by: Anusha Srivatsa <anusha.srivatsa@xxxxxxxxx>
>>
>>
>> Reviewed-by: Lucas De Marchi <lucas.demarchi@xxxxxxxxx>
>>
>> Lucas De Marchi
>>
>> >---
>> > drivers/gpu/drm/i915/gvt/handlers.c | 8 ++++----
>> > 1 file changed, 4 insertions(+), 4 deletions(-)
>> >
>> >diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
>> >index dda320749c65..33496397a74f 100644
>> >--- a/drivers/gpu/drm/i915/gvt/handlers.c
>> >+++ b/drivers/gpu/drm/i915/gvt/handlers.c
>> >@@ -3342,9 +3342,9 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
>> > MMIO_D(_MMIO(_PLANE_SURF_3_A), D_SKL_PLUS);
>> > MMIO_D(_MMIO(_PLANE_SURF_3_B), D_SKL_PLUS);
>> >
>> >- MMIO_D(CSR_SSP_BASE, D_SKL_PLUS);
>> >- MMIO_D(CSR_HTP_SKL, D_SKL_PLUS);
>> >- MMIO_D(CSR_LAST_WRITE, D_SKL_PLUS);
>> >+ MMIO_D(DMC_SSP_BASE, D_SKL_PLUS);
>> >+ MMIO_D(DMC_HTP_SKL, D_SKL_PLUS);
>> >+ MMIO_D(DMC_LAST_WRITE, D_SKL_PLUS);
>> >
>> > MMIO_DFH(BDW_SCRATCH1, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>> >
>> >@@ -3655,7 +3655,7 @@ void intel_gvt_clean_mmio_info(struct intel_gvt *gvt)
>> > * otherwise, need to update cmd_reg_handler in cmd_parser.c
>> > */
>> > static struct gvt_mmio_block mmio_blocks[] = {
>> >- {D_SKL_PLUS, _MMIO(CSR_MMIO_START_RANGE), 0x3000, NULL, NULL},
>> >+ {D_SKL_PLUS, _MMIO(DMC_MMIO_START_RANGE), 0x3000, NULL, NULL},
>> > {D_ALL, _MMIO(MCHBAR_MIRROR_BASE_SNB), 0x40000, NULL, NULL},
>> > {D_ALL, _MMIO(VGT_PVINFO_PAGE), VGT_PVINFO_SIZE,
>> > pvinfo_mmio_read, pvinfo_mmio_write},
>> >--
>> >2.25.0
>> >
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--
Jani Nikula, Intel Open Source Graphics Center
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