On Thu, 2021-05-06 at 00:01 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> Apparently we have discovered another way to hit the dreaded
> top of screen FBC corruption on GLK. Previously we thought it
> was limited to some combination of FBC nuke+disable+plane update
> during the same frame, for which we have the extra vblank wait
> as a workaround. But looks like it can somehow be hit even
> without the FBC disable.
>
> Skipping the extra manual nuke immediately after page flips seems
> to cure this. The manual nuke shouldn't be needed anyway since the
> flip itself will already cause a nuke. I suppose this means it might
> still be possible to hit this if you mix page flips and frontbuffer
> rendering in clever ways, but at least it's a bit less likely now.
makes sense, Reviewed-by: José Roberto de Souza <jose.souza@xxxxxxxxx>
You missed your Signed-off-by here.
> ---
> drivers/gpu/drm/i915/display/intel_fbc.c | 18 +++++++++++-------
> 1 file changed, 11 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> index b2f3ac846f5b..3251403b521f 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -233,7 +233,8 @@ static void intel_fbc_recompress(struct drm_i915_private *dev_priv)
>
> static void ilk_fbc_activate(struct drm_i915_private *dev_priv)
> {
> - struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
> + struct intel_fbc *fbc = &dev_priv->fbc;
> + struct intel_fbc_reg_params *params = &fbc->params;
> u32 dpfc_ctl;
> int threshold = dev_priv->fbc.threshold;
>
> @@ -276,7 +277,8 @@ static void ilk_fbc_activate(struct drm_i915_private *dev_priv)
> /* enable it... */
> intel_de_write(dev_priv, ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
>
> - intel_fbc_recompress(dev_priv);
> + if (!fbc->active)
> + intel_fbc_recompress(dev_priv);
> }
>
> static void ilk_fbc_deactivate(struct drm_i915_private *dev_priv)
> @@ -298,7 +300,8 @@ static bool ilk_fbc_is_active(struct drm_i915_private *dev_priv)
>
> static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
> {
> - struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
> + struct intel_fbc *fbc = &dev_priv->fbc;
> + struct intel_fbc_reg_params *params = &fbc->params;
> u32 dpfc_ctl;
> int threshold = dev_priv->fbc.threshold;
>
> @@ -350,7 +353,8 @@ static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
>
> intel_de_write(dev_priv, ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
>
> - intel_fbc_recompress(dev_priv);
> + if (!fbc->active)
> + intel_fbc_recompress(dev_priv);
> }
>
> static bool intel_fbc_hw_is_active(struct drm_i915_private *dev_priv)
> @@ -369,9 +373,6 @@ static void intel_fbc_hw_activate(struct drm_i915_private *dev_priv)
>
> trace_intel_fbc_activate(fbc->crtc);
>
> - fbc->active = true;
> - fbc->activated = true;
> -
> if (DISPLAY_VER(dev_priv) >= 7)
> gen7_fbc_activate(dev_priv);
> else if (DISPLAY_VER(dev_priv) >= 5)
> @@ -380,6 +381,9 @@ static void intel_fbc_hw_activate(struct drm_i915_private *dev_priv)
> g4x_fbc_activate(dev_priv);
> else
> i8xx_fbc_activate(dev_priv);
> +
> + fbc->active = true;
> + fbc->activated = true;
> }
>
> static void intel_fbc_hw_deactivate(struct drm_i915_private *dev_priv)
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