Am Thu, 13 May 2021 07:30:17 -0400
schrieb Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>:
> On Thu, May 13, 2021 at 10:18:49AM +1000, Dave Airlie wrote:
> > Reviewed-by: Dave Airlie <airlied@xxxxxxxxxx>
> >
> > Can we get this fix in, having a regression spanning 3 kernels
> > isn't a good look, we can work out why it matters later in life if
> > anyone cares.
>
> Agreed and pushed do drm-intel-next.
What's the status here? I can't seem to find the fix in drm-intel-next.
- Simon
>
> This triggered me to do an archeology work here and I found a possible
> alternative for ILK:
>
> +#define HIZ_UNIT_CLOCK_GATE_DISABLE REG_BIT(5)
>
> #define FDI_PLL_FREQ_CTL _MMIO(0x46030)
> #define FDI_PLL_FREQ_CHANGE_REQUEST (1 << 24)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c
> b/drivers/gpu/drm/i915/intel_pm.c index 06d5b7cc8b62..6316b70978f7
> 100644 --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -6892,8 +6892,11 @@ static void ilk_init_clock_gating(struct
> drm_i915_private *dev_priv) intel_uncore_write(&dev_priv->uncore,
> PCH_3DCGDIS0, MARIUNIT_CLOCK_GATE_DISABLE |
> SVSMUNIT_CLOCK_GATE_DISABLE);
> +
> + /* WaDisableHizUnitClockGating:ilk */
> intel_uncore_write(&dev_priv->uncore, PCH_3DCGDIS1,
> - VFMUNIT_CLOCK_GATE_DISABLE);
> + VFMUNIT_CLOCK_GATE_DISABLE |
> + HIZ_UNIT_CLOCK_GATE_DISABLE);
>
> however I couldn't find anything for Baytrail, so let's move with this
> one for now.
>
> >
> > Dave.
> >
> > On Tue, 27 Apr 2021 at 00:31, Simon Rettberg
> > <simon.rettberg@xxxxxxxxxxxxxxxxxx> wrote:
> > >
> > > When resetting CACHE_MODE registers, don't enable HiZ Raw Stall
> > > Optimization on Ivybridge GT1 and Baytrail, as it causes severe
> > > glitches when rendering any kind of 3D accelerated content.
> > > This optimization is disabled on these platforms by default
> > > according to official documentation from 01.org.
> > >
> > > Fixes: ef99a60ffd9b ("drm/i915/gt: Clear CACHE_MODE prior to
> > > clearing residuals") Fixes: 520d05a77b28 ("drm/i915/gt: Clear
> > > CACHE_MODE prior to clearing residuals") BugLink:
> > > https://gitlab.freedesktop.org/drm/intel/-/issues/3081 BugLink:
> > > https://gitlab.freedesktop.org/drm/intel/-/issues/3404 BugLink:
> > > https://gitlab.freedesktop.org/drm/intel/-/issues/3071
> > > Reviewed-By: Manuel Bentele <development@xxxxxxxxxxxxxxxxx>
> > > Signed-off-by: Simon Rettberg <simon.rettberg@xxxxxxxxxxxxxxxxxx>
> > > --- drivers/gpu/drm/i915/gt/gen7_renderclear.c | 5 ++++-
> > > 1 file changed, 4 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/gt/gen7_renderclear.c
> > > b/drivers/gpu/drm/i915/gt/gen7_renderclear.c index
> > > de575fdb0..21f08e538 100644 ---
> > > a/drivers/gpu/drm/i915/gt/gen7_renderclear.c +++
> > > b/drivers/gpu/drm/i915/gt/gen7_renderclear.c @@ -397,7 +397,10 @@
> > > static void emit_batch(struct i915_vma * const vma,
> > > gen7_emit_pipeline_invalidate(&cmds); batch_add(&cmds,
> > > MI_LOAD_REGISTER_IMM(2)); batch_add(&cmds,
> > > i915_mmio_reg_offset(CACHE_MODE_0_GEN7));
> > > - batch_add(&cmds, 0xffff0000);
> > > + batch_add(&cmds, 0xffff0000 |
> > > + ((IS_IVB_GT1(i915) ||
> > > IS_VALLEYVIEW(i915)) ?
> > > + HIZ_RAW_STALL_OPT_DISABLE :
> > > + 0));
> > > batch_add(&cmds, i915_mmio_reg_offset(CACHE_MODE_1));
> > > batch_add(&cmds, 0xffff0000 |
> > > PIXEL_SUBSPAN_COLLECT_OPT_DISABLE);
> > > gen7_emit_pipeline_invalidate(&cmds); --
> > > 2.25.1
> > >
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
