On Sat, Apr 17, 2021 at 05:21:26PM -0700, José Roberto de Souza wrote: > This workaround requires that VIDEO_DIP_ENABLE_VSC_HSW is never set > with PSR. > > BSpec: 54369 > BSpec: 54077 Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@xxxxxxxxx> > Cc: Matt Atwood <matthew.s.atwood@xxxxxxxxx> > Cc: Gwan-gyeong Mun <gwan-gyeong.mun@xxxxxxxxx> > Signed-off-by: José Roberto de Souza <jose.souza@xxxxxxxxx> > --- > drivers/gpu/drm/i915/display/intel_hdmi.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c > index de7328685d40..3876a52642a4 100644 > --- a/drivers/gpu/drm/i915/display/intel_hdmi.c > +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c > @@ -531,6 +531,11 @@ void hsw_write_infoframe(struct intel_encoder *encoder, > hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2), > 0); > > + /* Wa_14013475917 */ > + if (DISPLAY_VER(dev_priv) == 13 && crtc_state->has_psr && > + type == DP_SDP_VSC) > + return; > + > val |= hsw_infoframe_enable(type); > intel_de_write(dev_priv, ctl_reg, val); > intel_de_posting_read(dev_priv, ctl_reg); > -- > 2.31.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
