On Sat, Apr 17, 2021 at 05:21:22PM -0700, José Roberto de Souza wrote:
> So far if we had a mismatch between the state asked and what was
> programmed in hardware for PSR, this mismatch would go unnoticed.
>
> So here adding the PSR to the hardware configuration readout,
> EDP_PSR_CTL and EDP_PSR2_CTL can't be directly read because its state
> flips due to other factors like frontbuffer modifications and CRC.
>
Minor nit-pick below with that fixed
Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@xxxxxxxxx>
> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@xxxxxxxxx>
> Signed-off-by: José Roberto de Souza <jose.souza@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 2 +
> drivers/gpu/drm/i915/display/intel_display.c | 5 +++
> drivers/gpu/drm/i915/display/intel_psr.c | 47 ++++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_psr.h | 3 ++
> 4 files changed, 57 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 4ef573883412..f69ed3c4c30a 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3707,6 +3707,8 @@ static void intel_ddi_get_config(struct intel_encoder *encoder,
>
> intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA);
> intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
> +
> + intel_psr_get_config(encoder, pipe_config);
> }
>
> void intel_ddi_get_clock(struct intel_encoder *encoder,
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 9c13d0ac022b..ecdca523e364 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -8350,6 +8350,11 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
> PIPE_CONF_CHECK_I(vrr.flipline);
> PIPE_CONF_CHECK_I(vrr.pipeline_full);
>
> + PIPE_CONF_CHECK_BOOL(has_psr);
> + PIPE_CONF_CHECK_BOOL(has_psr2);
> + PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch);
> + PIPE_CONF_CHECK_I(dc3co_exitline);
> +
> #undef PIPE_CONF_CHECK_X
> #undef PIPE_CONF_CHECK_I
> #undef PIPE_CONF_CHECK_BOOL
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 4ad756e238c5..bd7997a3ef7c 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -886,6 +886,53 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
> crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
> }
>
> +void intel_psr_get_config(struct intel_encoder *encoder,
> + struct intel_crtc_state *pipe_config)
> +{
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> + struct intel_dp *intel_dp;
> + u32 val;
> +
> + if (!dig_port)
> + return;
> +
> + intel_dp = &dig_port->dp;
> + if (!CAN_PSR(intel_dp))
> + return;
> +
> + mutex_lock(&intel_dp->psr.lock);
> + if (!intel_dp->psr.enabled) {
goto unlock: should suffice here instead of unlock and return.
-RK
> + mutex_unlock(&intel_dp->psr.lock);
> + return;
> + }
> +
> + /*
> + * Not possible to read EDP_PSR/PSR2_CTL registers as it is
> + * enabled/disabled because of frontbuffer tracking and others.
> + */
> + pipe_config->has_psr = true;
> + pipe_config->has_psr2 = intel_dp->psr.psr2_enabled;
> + pipe_config->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
> +
> + if (!intel_dp->psr.psr2_enabled)
> + goto unlock;
> +
> + if (HAS_PSR2_SEL_FETCH(dev_priv)) {
> + val = intel_de_read(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder));
> + if (val & PSR2_MAN_TRK_CTL_ENABLE)
> + pipe_config->enable_psr2_sel_fetch = true;
> + }
> +
> + if (DISPLAY_VER(dev_priv) >= 12) {
> + val = intel_de_read(dev_priv, EXITLINE(intel_dp->psr.transcoder));
> + val &= EXITLINE_MASK;
> + pipe_config->dc3co_exitline = val;
> + }
> +unlock:
> + mutex_unlock(&intel_dp->psr.lock);
> +}
> +
> static void intel_psr_activate(struct intel_dp *intel_dp)
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
> index 0491a49ffd50..e3db85e97f4c 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> @@ -17,6 +17,7 @@ struct intel_crtc;
> struct intel_atomic_state;
> struct intel_plane_state;
> struct intel_plane;
> +struct intel_encoder;
>
> void intel_psr_init_dpcd(struct intel_dp *intel_dp);
> void intel_psr_enable(struct intel_dp *intel_dp,
> @@ -37,6 +38,8 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
> void intel_psr_init(struct intel_dp *intel_dp);
> void intel_psr_compute_config(struct intel_dp *intel_dp,
> struct intel_crtc_state *crtc_state);
> +void intel_psr_get_config(struct intel_encoder *encoder,
> + struct intel_crtc_state *pipe_config);
> void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir);
> void intel_psr_short_pulse(struct intel_dp *intel_dp);
> void intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state);
> --
> 2.31.1
>
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