Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@xxxxxxxxx> On Wed, 2021-05-05 at 14:38 -0700, José Roberto de Souza wrote: > The implementation of two workarounds are missing causing failures > in CI with pre-production HW. > > Cc: Gwan-gyeong Mun <gwan-gyeong.mun@xxxxxxxxx> > Signed-off-by: José Roberto de Souza <jose.souza@xxxxxxxxx> > --- > drivers/gpu/drm/i915/display/intel_psr.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > b/drivers/gpu/drm/i915/display/intel_psr.c > index e3c30dcadcd1..406ba9a712a8 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.c > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > @@ -720,6 +720,13 @@ static bool > intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp, > } > } > > + /* Wa_14010254185 Wa_14010103792 */ > + if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B1)) { > + drm_dbg_kms(&dev_priv->drm, > + "PSR2 sel fetch not enabled, missing the > implementation of WAs\n"); > + return false; > + } > + > return crtc_state->enable_psr2_sel_fetch = true; > } > _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx