| Series: | Introduce Alder Lake-P (rev2) |
| URL: | https://patchwork.freedesktop.org/series/87897/ |
| State: | success |
| Details: | https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19858/index.html |
CI Bug Log - changes from CI_DRM_9895 -> Patchwork_19858
Summary
SUCCESS
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19858/index.html
Known issues
Here are the changes found in Patchwork_19858 that come from known issues:
IGT changes
Issues hit
-
igt@gem_exec_fence@basic-busy@bcs0:
- fi-kbl-soraka: NOTRUN -> SKIP (fdo#109271) +24 similar issues
-
igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka: NOTRUN -> SKIP (fdo#109271 / i915#2190)
-
igt@gem_render_tiled_blits@basic:
- fi-tgl-y: PASS -> DMESG-WARN (i915#402)
-
igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka: NOTRUN -> DMESG-FAIL (i915#1886 / i915#2291)
-
igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-soraka: NOTRUN -> SKIP (fdo#109271 / fdo#111827) +8 similar issues
-
igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-kbl-soraka: NOTRUN -> SKIP (fdo#109271 / i915#533)
Possible fixes
-
igt@gem_exec_suspend@basic-s3:
- fi-tgl-y: DMESG-WARN (i915#2411 / i915#402) -> PASS
-
igt@i915_getparams_basic@basic-subslice-total:
- fi-tgl-y: DMESG-WARN (i915#402) -> PASS
Participating hosts (46 -> 42)
Additional (1): fi-kbl-soraka
Missing (5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-bdw-samus fi-snb-2600
Build changes
- Linux: CI_DRM_9895 -> Patchwork_19858
CI-20190529: 20190529
CI_DRM_9895: bb187b1b292c637c3ef195f46d6e5c74f60df8f4 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6046: e76039273b1524147c43dba061756f06003d56ae @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19858: d6cca7188c328b11c07372df414c6a6fdbcf58ab @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
d6cca7188c32 drm/i915/display/adl_p: Implement PSR changes
e4ebbafb718a drm/i915/perf: Enable OA formats for ADL_P
4c6bdb3a898f drm/i915/display/adl_p: Remove CCS support
db10565794e4 drm/i915/display/adl_p: Implement Wa_22011320316
59365b8cc821 drm/i915/adl_p: Implement Wa_22011091694
b8c997a50244 drm/i915/adl_p: Update memory bandwidth parameters
08ab2ee39ff8 drm/i915/adlp: Add PIPE_MISC2 programming
4b22d79b8150 drm/i915/bigjoiner: atomic commit changes for uncompressed joiner
a3fcb1f129cf drm/i915/bigjoiner: Avoid dsc_compute_config for uncompressed bigjoiner
43b982e116e1 drm/i915/bigjoiner: Mode validation with uncompressed pipe joiner
87b27bda44f9 drm/i915/adl_p: Add PLL Support
a826d07dfb49 drm/i915/adl_p: Enable/disable loadgen sharing
741d91ba895c drm/i915/adl_p: Define and use ADL-P specific DP translation tables
172c5e1265df drm/i915/adlp: Define GuC/HuC for Alderlake_P
22f7579ed8ae drm/i915/adl_p: Add initial ADL_P Workarounds
6ae0308eb78c drm/i915/adl_p: Tx escape clock with DSI
b6f7ef6a2700 drm/i915/adl_p: MBUS programming
1d59d31ac064 drm/i915: Move intel_modeset_all_pipes()
3085ffa95a6c drm/i915: Introduce MBUS relative dbuf offsets
1934f7197873 drm/i915/adl_p: Add ddb allocation support
2a5c21d0cfe3 drm/i915/adl_p: Don't config MBUS and DBUF during display initialization
9466294b8073 drm/i915/adl_p: Enable modular fia
b561e55ad7ed drm/i915/adl_p: Implement TC sequences
37791d3e9b57 drm/i915/adl_p: Handle TC cold
105d4ea67ba9 drm/i915/display/tc: Rename safe_mode functions ownership
7d3738ea84a7 drm/i915/adl_p: Add cdclk support for ADL-P
e0b3264bd0aa drm/i915/adl_p: Setup ports/phys
0829e10a0986 drm/i915/adl_p: Load DMC
0a8ca545c487 drm/i915/adl_p: Extend PLANE_WM bits for blocks & lines
cc43924843e1 drm/i915/adl_p: Add dedicated SAGV watermarks
854bc1ad1d76 drm/i915/adl_p: Add PCH support
eccf706853f7 drm/i915/adl_p: ADL_P device info enabling
0d14daf39c18 drm/i915/adl_p: Add PCI Devices IDs
f57027254bab drm/i915/xelpd: Add VRR guardband for VRR CTL
929cf2a04dfd drm/i915/xelpd: Add rc_qp_table for rcparams calculation
60bacc26c600 drm/i915/xelpd: Calculate VDSC RC parameters
47902928aede drm/i915: Get slice height before computing rc params
fe6932615988 drm/i915/xelpd: Support DP1.4 compression BPPs
30661a762a91 drm/i915/display/dsc: Refactor intel_dp_dsc_compute_bpp
1649e5409acb drm/i915/xelpd: Add Wa_14011503030
37130f19e90e drm/i915/xelpd: Required bandwidth increases when VT-d is active
a0d6295b5373 drm/i915/xelpd: Increase maximum watermark lines to 255
1e2bd7a5af67 drm/i915/xelpd: Handle LPSP for XE_LPD
7f1092ee9104 drm/i915/xelpd: Add XE_LPD power wells
b9c9d9f72027 drm/i915/xelpd: Handle new location of outputs D and E
9cd15eaee7ad drm/i915/xelpd: Support 128k plane stride
0bdd697a29f1 drm/i915/xelpd: Define plane capabilities
342f5a714f77 drm/i915/xelpd: Enhanced pipe underrun reporting
06a6b306bb11 drm/i915/xelpd: Handle proper AUX interrupt bits
c64437e8902e drm/i915/xelpd: add XE_LPD display characteristics
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