From: José Roberto de Souza <jose.souza@xxxxxxxxx> Alderlake-P don't have programing sequences for MBUS or DBUF during display initializaiton, instead it requires programing to those registers during modeset because it to depend on the pipes left enabled. Bspec: 49213 Cc: Matt Roper <matthew.d.roper@xxxxxxxxx> Signed-off-by: José Roberto de Souza <jose.souza@xxxxxxxxx> Signed-off-by: Clinton Taylor <Clinton.A.Taylor@xxxxxxxxx> Signed-off-by: Matt Roper <matthew.d.roper@xxxxxxxxx> --- drivers/gpu/drm/i915/display/intel_display_power.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 3e407d0bf363..969cde822e1e 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -5249,6 +5249,9 @@ static void gen12_dbuf_slices_config(struct drm_i915_private *dev_priv) const int num_slices = INTEL_INFO(dev_priv)->num_supported_dbuf_slices; enum dbuf_slice slice; + if (IS_ALDERLAKE_P(dev_priv)) + return; + for (slice = DBUF_S1; slice < (DBUF_S1 + num_slices); slice++) intel_de_rmw(dev_priv, DBUF_CTL_S(slice), DBUF_TRACKER_STATE_SERVICE_MASK, @@ -5260,6 +5263,9 @@ static void icl_mbus_init(struct drm_i915_private *dev_priv) unsigned long abox_regs = INTEL_INFO(dev_priv)->abox_mask; u32 mask, val, i; + if (IS_ALDERLAKE_P(dev_priv)) + return; + mask = MBUS_ABOX_BT_CREDIT_POOL1_MASK | MBUS_ABOX_BT_CREDIT_POOL2_MASK | MBUS_ABOX_B_CREDIT_MASK | -- 2.25.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
