On Mon, Mar 22, 2021 at 08:00:05PM +0530, Bhanuprakash Modem wrote:
> For Cherryview, add hw read out to create hw blob of ctm coeff
> values.
>
> Cc: Swati Sharma <swati2.sharma@xxxxxxxxx>
> Cc: Uma Shankar <uma.shankar@xxxxxxxxx>
> Signed-off-by: Bhanuprakash Modem <bhanuprakash.modem@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_color.c | 47 ++++++++++++++++++++++
> 1 file changed, 47 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> index 54dfd3523272..15f97fbb77b3 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -1943,6 +1943,52 @@ static void chv_read_luts(struct intel_crtc_state *crtc_state)
> i965_read_luts(crtc_state);
> }
>
> +static struct drm_property_blob *chv_read_cgm_ctm(struct intel_crtc *crtc)
> +{
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + enum pipe pipe = crtc->pipe;
> + struct drm_property_blob *blob;
> + struct drm_color_ctm *ctm;
> + u32 temp;
> +
> + blob = drm_property_create_blob(&dev_priv->drm,
> + sizeof(struct drm_color_ctm),
> + NULL);
> + if (IS_ERR(blob))
> + return NULL;
> +
> + ctm = blob->data;
> +
> + temp = intel_de_read(dev_priv, CGM_PIPE_CSC_COEFF01(pipe));
> + ctm->matrix[0] = (temp >> 16) & 0xffff;
> + ctm->matrix[1] = temp & 0xffff;
We can't store hardware specific junk into the ctm. It needs to get
converted to the proper format.
Would also be a good time to fix the CHV CSC programming to handle
negative values correct, and should probably extend the test cases
to actually catch that particular failure...
> +
> + temp = intel_de_read(dev_priv, CGM_PIPE_CSC_COEFF23(pipe));
> + ctm->matrix[2] = (temp >> 16) & 0xffff;
> + ctm->matrix[3] = temp & 0xffff;
> +
> + temp = intel_de_read(dev_priv, CGM_PIPE_CSC_COEFF45(pipe));
> + ctm->matrix[4] = (temp >> 16) & 0xffff;
> + ctm->matrix[5] = temp & 0xffff;
> +
> + temp = intel_de_read(dev_priv, CGM_PIPE_CSC_COEFF67(pipe));
> + ctm->matrix[6] = (temp >> 16) & 0xffff;
> + ctm->matrix[7] = temp & 0xffff;
> +
> + temp = intel_de_read(dev_priv, CGM_PIPE_CSC_COEFF8(pipe));
> + ctm->matrix[8] = (temp >> 16) & 0xffff;
> +
> + return blob;
> +}
> +
> +static void chv_read_csc(struct intel_crtc_state *crtc_state)
> +{
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +
> + if (crtc_state->cgm_mode & CGM_PIPE_MODE_CSC)
> + crtc_state->hw.ctm = chv_read_cgm_ctm(crtc);
> +}
> +
> static struct drm_property_blob *ilk_read_lut_8(struct intel_crtc *crtc)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> @@ -2145,6 +2191,7 @@ void intel_color_init(struct intel_crtc *crtc)
> dev_priv->display.color_commit = i9xx_color_commit;
> dev_priv->display.load_luts = chv_load_luts;
> dev_priv->display.read_luts = chv_read_luts;
> + dev_priv->display.read_csc = chv_read_csc;
> } else if (INTEL_GEN(dev_priv) >= 4) {
> dev_priv->display.color_check = i9xx_color_check;
> dev_priv->display.color_commit = i9xx_color_commit;
> --
> 2.20.1
>
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--
Ville Syrjälä
Intel
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