For icl+, add hw read out to create hw blob of ctm coeff values. Cc: Swati Sharma <swati2.sharma@xxxxxxxxx> Cc: Uma Shankar <uma.shankar@xxxxxxxxx> Signed-off-by: Bhanuprakash Modem <bhanuprakash.modem@xxxxxxxxx> --- drivers/gpu/drm/i915/display/intel_color.c | 55 ++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 877833f294bb..8f9727553c45 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -396,6 +396,60 @@ static void icl_load_csc_matrix(const struct intel_crtc_state *crtc_state) crtc_state->csc_mode); } +static struct drm_property_blob *icl_read_output_csc_matrix(struct intel_crtc *crtc) +{ + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + enum pipe pipe = crtc->pipe; + struct drm_property_blob *blob; + struct drm_color_ctm *ctm; + u32 temp; + + blob = drm_property_create_blob(&dev_priv->drm, + sizeof(struct drm_color_ctm), + NULL); + if (IS_ERR(blob)) + return NULL; + + ctm = blob->data; + + temp = intel_de_read(dev_priv, PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe)); + ctm->matrix[0] = (temp >> 16) & 0xffff; + ctm->matrix[1] = temp & 0xffff; + + temp = intel_de_read(dev_priv, PIPE_CSC_OUTPUT_COEFF_BY(pipe)); + ctm->matrix[2] = (temp >> 16) & 0xffff; + + temp = intel_de_read(dev_priv, PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe)); + ctm->matrix[3] = (temp >> 16) & 0xffff; + ctm->matrix[4] = temp & 0xffff; + + temp = intel_de_read(dev_priv, PIPE_CSC_OUTPUT_COEFF_BU(pipe)); + ctm->matrix[5] = (temp >> 16) & 0xffff; + + temp = intel_de_read(dev_priv, PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe)); + ctm->matrix[6] = (temp >> 16) & 0xffff; + ctm->matrix[7] = temp & 0xffff; + + temp = intel_de_read(dev_priv, PIPE_CSC_OUTPUT_COEFF_BV(pipe)); + ctm->matrix[8] = (temp >> 16) & 0xffff; + + return blob; +} + +static void icl_read_csc(struct intel_crtc_state *crtc_state) +{ + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + + if (!crtc_state->csc_enable) + return; + + if (crtc_state->csc_mode & ICL_CSC_ENABLE) + crtc_state->hw.ctm = ilk_read_csc_matrix(crtc); + + if (crtc_state->csc_mode & ICL_OUTPUT_CSC_ENABLE) + crtc_state->hw.ctm = icl_read_output_csc_matrix(crtc); +} + static void chv_csc_convert_ctm(const struct drm_color_ctm *ctm, u16 coeffs[9]) { int i; @@ -2271,6 +2325,7 @@ void intel_color_init(struct intel_crtc *crtc) if (INTEL_GEN(dev_priv) >= 11) { dev_priv->display.load_luts = icl_load_luts; dev_priv->display.read_luts = icl_read_luts; + dev_priv->display.read_csc = icl_read_csc; } else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) { dev_priv->display.load_luts = glk_load_luts; dev_priv->display.read_luts = glk_read_luts; -- 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx