> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Matt
> Roper
> Sent: Thursday, March 11, 2021 2:36 PM
> To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> Subject: [PATCH 26/56] drm/i915/adl_p: Add PCH support
>
> From: Clinton Taylor <Clinton.A.Taylor@xxxxxxxxx>
>
> Add ADP-P PCH device ID and assign as ADL PCH if found. Previously we
> would assign the DDC pin map based on the PCH, but it can also change
> based on the CPU. From Bspec 20124: "The physical port to pin pair mapping
> are defined in the Bspec per PCH. Mapping can further change based on CPU
> Si used as CPU and PCH can be mixed and matched".
>
> Bspec: 20124
> Cc: Matt Atwood <matthew.s.atwood@xxxxxxxxx>
> Cc: Matt Roper <matthew.d.roper@xxxxxxxxx>
> Signed-off-by: Clinton Taylor <Clinton.A.Taylor@xxxxxxxxx>
> Signed-off-by: Matt Roper <matthew.d.roper@xxxxxxxxx>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_bios.c | 2 +-
> drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +-
> drivers/gpu/drm/i915/intel_pch.c | 6 ++++--
> drivers/gpu/drm/i915/intel_pch.h | 1 +
> 4 files changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
> b/drivers/gpu/drm/i915/display/intel_bios.c
> index e4cef54726b4..5f8d14be1265 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -1649,7 +1649,7 @@ static u8 map_ddc_pin(struct drm_i915_private
> *dev_priv, u8 vbt_pin)
> const u8 *ddc_pin_map;
> int n_entries;
>
> - if (HAS_PCH_ADP(dev_priv)) {
> + if (IS_ALDERLAKE_S(dev_priv)) {
> ddc_pin_map = adls_ddc_pin_map;
> n_entries = ARRAY_SIZE(adls_ddc_pin_map);
> } else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) { diff --git
> a/drivers/gpu/drm/i915/display/intel_hdmi.c
> b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index 4f285c7d54c4..2a2b01026564 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -3213,7 +3213,7 @@ static u8 intel_hdmi_ddc_pin(struct intel_encoder
> *encoder)
> return ddc_pin;
> }
>
> - if (HAS_PCH_ADP(dev_priv))
> + if (IS_ALDERLAKE_S(dev_priv))
> ddc_pin = adls_port_to_ddc_pin(dev_priv, port);
> else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
> ddc_pin = dg1_port_to_ddc_pin(dev_priv, port); diff --git
> a/drivers/gpu/drm/i915/intel_pch.c b/drivers/gpu/drm/i915/intel_pch.c
> index 7476f0e063c6..98a17dd1bda4 100644
> --- a/drivers/gpu/drm/i915/intel_pch.c
> +++ b/drivers/gpu/drm/i915/intel_pch.c
> @@ -130,8 +130,10 @@ intel_pch_type(const struct drm_i915_private
> *dev_priv, unsigned short id)
> drm_WARN_ON(&dev_priv->drm, !IS_JSL_EHL(dev_priv));
> return PCH_JSP;
> case INTEL_PCH_ADP_DEVICE_ID_TYPE:
> + case INTEL_PCH_ADP2_DEVICE_ID_TYPE:
> drm_dbg_kms(&dev_priv->drm, "Found Alder Lake PCH\n");
> - drm_WARN_ON(&dev_priv->drm,
> !IS_ALDERLAKE_S(dev_priv));
> + drm_WARN_ON(&dev_priv->drm,
> !IS_ALDERLAKE_S(dev_priv) &&
> + !IS_ALDERLAKE_P(dev_priv));
> return PCH_ADP;
> default:
> return PCH_NONE;
> @@ -161,7 +163,7 @@ intel_virt_detect_pch(const struct drm_i915_private
> *dev_priv,
> * make an educated guess as to which PCH is really there.
> */
>
> - if (IS_ALDERLAKE_S(dev_priv))
> + if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv))
> id = INTEL_PCH_ADP_DEVICE_ID_TYPE;
> else if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv))
> id = INTEL_PCH_TGP_DEVICE_ID_TYPE;
> diff --git a/drivers/gpu/drm/i915/intel_pch.h
> b/drivers/gpu/drm/i915/intel_pch.h
> index 7318377503b0..e2f3f30c6445 100644
> --- a/drivers/gpu/drm/i915/intel_pch.h
> +++ b/drivers/gpu/drm/i915/intel_pch.h
> @@ -55,6 +55,7 @@ enum intel_pch {
> #define INTEL_PCH_JSP_DEVICE_ID_TYPE 0x4D80
> #define INTEL_PCH_JSP2_DEVICE_ID_TYPE 0x3880
> #define INTEL_PCH_ADP_DEVICE_ID_TYPE 0x7A80
> +#define INTEL_PCH_ADP2_DEVICE_ID_TYPE 0x5180
> #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
> #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
> #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35
> has 2918 */
> --
> 2.25.4
>
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