✗ Fi.CI.BAT: failure for Introduce Alder Lake-P

[Patchwork <patchwork@xxxxxxxxxxxxxxxxxxxxxx>]

Title: Project List - Patchwork

Patch Details

Series:	Introduce Alder Lake-P
URL:	https://patchwork.freedesktop.org/series/87897/
State:	failure
Details:	https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19786/index.html

CI Bug Log - changes from CI_DRM_9851 -> Patchwork_19786

Summary

FAILURE

Serious unknown changes coming with Patchwork_19786 absolutely need to be
verified manually.

If you think the reported changes have nothing to do with the changes
introduced in Patchwork_19786, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.

External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19786/index.html

Possible new issues

Here are the unknown changes that may have been introduced in Patchwork_19786:

IGT changes

Possible regressions

• igt@core_hotunplug@unbind-rebind:

  • fi-bwr-2160: PASS -> FAIL

• igt@runner@aborted:

  • fi-cml-u2: NOTRUN -> FAIL

  • fi-tgl-u2: NOTRUN -> FAIL

Known issues

Here are the changes found in Patchwork_19786 that come from known issues:

IGT changes

Issues hit

• igt@amdgpu/amd_basic@userptr:

  • fi-byt-j1900: NOTRUN -> SKIP (fdo#109271) +17 similar issues

• igt@gem_exec_gttfill@basic:

  • fi-kbl-8809g: PASS -> TIMEOUT (i915#3145)

Possible fixes

• igt@gem_linear_blits@basic:

  • fi-kbl-8809g: TIMEOUT (i915#2502 / i915#3145) -> PASS +1 similar issue

• igt@gem_tiled_fence_blits@basic:

  • fi-kbl-8809g: TIMEOUT (i915#3145) -> PASS

• igt@gem_wait@busy@all:

  • fi-bsw-nick: FAIL (i915#3177) -> PASS

• igt@i915_pm_rpm@module-reload:

  • fi-byt-j1900: INCOMPLETE (i915#142 / i915#2405) -> PASS

Warnings

• igt@runner@aborted:
  • fi-icl-u2: FAIL (i915#1814) -> FAIL (i915#1569 / k.org#202973)

{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).

Participating hosts (46 -> 39)

Missing (7): fi-ilk-m540 fi-hsw-4200u fi-bsw-n3050 fi-glk-dsi fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus

Build changes

• Linux: CI_DRM_9851 -> Patchwork_19786

CI-20190529: 20190529
CI_DRM_9851: 3c654b84957a19021def19bba396189409f197ea @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6030: e11e4bfb91fec9af71c3909996c66e5666270e07 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19786: ff4d1fd19abda93fafaec66c226bd41895c64fff @ git://anongit.freedesktop.org/gfx-ci/linux

== Linux commits ==

ff4d1fd19abd drm/i915/display/adl_p: Implement PSR changes
8e8789fb3382 drm/i915/perf: Enable OA formats for ADL_P
5f5ddd87a7d9 drm/i915/display/adl_p: Remove CCS support
80727a5175f3 drm/i915/display/adl_p: Implement Wa_22011320316
338170857dd4 drm/i915/adl_p: Implement Wa_22011091694
7ae8fa32c79f drm/i915/adl_p: Update memory bandwidth parameters
0f2911a4def4 drm/i915/adlp: Add PIPE_MISC2 programming
a967b8f0d577 drm/i915/bigjoiner: atomic commit changes for uncompressed joiner
f6779a65ec33 drm/i915/bigjoiner: Avoid dsc_compute_config for uncompressed bigjoiner
f3adcffb1aee drm/i915/bigjoiner: Mode validation with uncompressed pipe joiner
24fddb894143 drm/i915/adl_p: Add PLL Support
4b31b97ab781 drm/i915/adl_p: Enable/disable loadgen sharing
b304533d0f55 drm/i915/adl_p: Define and use ADL-P specific DP translation tables
229748b64190 drm/i915/adlp: Define GuC/HuC for Alderlake_P
eaa274e708a8 drm/i915/adl_p: Add initial ADL_P Workarounds
bed8e7bb8774 drm/i915/adl_p: Tx escape clock with DSI
b7078c173757 drm/i915/adl_p: MBUS programming
33b7d6985cbf drm/i915: Move intel_modeset_all_pipes()
ece44a3951a4 drm/i915: Introduce MBUS relative dbuf offsets
d9c40cc5183b drm/i915/adl_p: Add ddb allocation support
7f6b13959baf drm/i915/adl_p: Don't config MBUS and DBUF during display initialization
76d78f0a89b0 drm/i915/adl_p: Enable modular fia
d3d588966024 drm/i915/adl_p: Implement TC sequences
1cc279b9a9ae drm/i915/adl_p: Handle TC cold
72da71eda198 drm/i915/display/tc: Rename safe_mode functions ownership
b88ec5ff4cf4 drm/i915/adl_p: Add cdclk support for ADL-P
53cbbdc4ce2b drm/i915/adl_p: Setup ports/phys
a31a27c201e3 drm/i915/adl_p: Load DMC
c8feb3de6d2f drm/i915/adl_p: Extend PLANE_WM bits for blocks & lines
e5d780a7e2c8 drm/i915/adl_p: Add dedicated SAGV watermarks
9a60ab0c7f6f drm/i915/adl_p: Add PCH support
3ca777b82d4f drm/i915/adl_p: ADL_P device info enabling
7c90acb36f4d drm/i915/adl_p: Add PCI Devices IDs
1a36ab332c53 drm/i915/xelpd: Add VRR guardband for VRR CTL
e545fc603067 drm/i915/xelpd: Add rc_qp_table for rcparams calculation
e1dce68d97ed drm/i915/xelpd: Calculate VDSC RC parameters
c9b04c68d8a0 drm/i915: Get slice height before computing rc params
ffeca9d43e30 drm/i915/xelpd: Support DP1.4 compression BPPs
c06f1cfdb54c drm/i915/display/dsc: Refactor intel_dp_dsc_compute_bpp
40c5437f3499 drm/i915/xelpd: Add Wa_14011503030
e280eb022d6d drm/i915/xelpd: Required bandwidth increases when VT-d is active
da736ae5f9ac drm/i915/xelpd: Increase maximum watermark lines to 255
206a1379e251 drm/i915/xelpd: Handle LPSP for XE_LPD
bc80bcbca1c1 drm/i915/xelpd: Add XE_LPD power wells
d770b6b8cd28 drm/i915/xelpd: Handle new location of outputs D and E
19b0bb00151b drm/i915/xelpd: Support 128k plane stride
a34d69c7ec8d drm/i915/xelpd: Define plane capabilities
3e432180467c drm/i915/xelpd: Enhanced pipe underrun reporting
2fd845823954 drm/i915/xelpd: Handle proper AUX interrupt bits
0afe26e7a99d drm/i915/xelpd: add XE_LPD display characteristics
a0318588a6b7 drm/i915/display: Simplify GLK display version tests
dd05f3125c5b drm/i915: Convert INTEL_GEN() to DISPLAY_VER() as appropriate in i915_irq.c
92d30df5de1c drm/i915: Convert INTEL_GEN() to DISPLAY_VER() as appropriate in intel_pm.c
4d46d9bc5a06 drm/i915/display: Eliminate most usage of INTEL_GEN()
8e54a5e601c5 drm/i915: Add DISPLAY_VER()
545bd02e1c9a drm/i915/display: Convert gen5/gen6 tests to IS_IRONLAKE/IS_SANDYBRIDGE

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