On Tue, 2021-02-23 at 15:38 +0530, Gupta, Anshuman wrote: > > > > -----Original Message----- > > From: Mun, Gwan-gyeong <gwan-gyeong.mun@xxxxxxxxx> > > Sent: Tuesday, February 23, 2021 3:00 AM > > To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx > > Cc: Gupta, Anshuman <anshuman.gupta@xxxxxxxxx>; Souza, Jose > > <jose.souza@xxxxxxxxx> > > Subject: [PATCH v3] drm/i915/display: Do not allow DC3CO if PSR SF > > is enabled > > > > Even though GEN12+ HW supports PSR + DC3CO, DMC's HW DC3CO exit > > mechanism has an issue with using of Selective Fecth and PSR2 > > manual tracking. > > And as some GEN12+ platforms (RKL, ADL-S) don't support PSR2 HW > > tracking, > > Selective Fetch will be enabled by default on that platforms. > > Therefore if the system enables PSR Selective Fetch / PSR manual > > tracking, it > > does not allow DC3CO dc state, in that case. > > > > When this DC3CO exit issue is addressed while PSR Selective Fetch > > is enabled, > > this restriction should be removed. > > > > v2: Address Jose's review comment. > > - Fix typo > > - Move check routine of DC3CO ability to > > tgl_dc3co_exitline_compute_config() > > v3: Change the check routine of enablement of psr2 sel fetch. > > (Jose) > > > > Cc: José Roberto de Souza <jose.souza@xxxxxxxxx> > > Cc: Anshuman Gupta <anshuman.gupta@xxxxxxxxx> > > Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@xxxxxxxxx> > > --- > > drivers/gpu/drm/i915/display/intel_psr.c | 7 +++++++ > > 1 file changed, 7 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > > b/drivers/gpu/drm/i915/display/intel_psr.c > > index 7c6e561f86c1..cd434285e3b7 100644 > > --- a/drivers/gpu/drm/i915/display/intel_psr.c > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > > @@ -654,6 +654,13 @@ tgl_dc3co_exitline_compute_config(struct > > intel_dp > > *intel_dp, > > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > > u32 exit_scanlines; > > > > + /* > > + * DMC's DC3CO exit mechanism has an issue with Selective > > Fecth > > + * TODO: when the issue is addressed, this restriction > > should be > > removed. > > + */ > Earlier when PSR2 H/W tracking was enabled, DC3CO exit and frame > updates works on it's own > Supported by DE engine and DMC firmware, but with selective fetch > enable as it disables the PSR2 H/W > Tracking. It requires to get sequence of DC3CO exit while PSR2 H/W > tracking disabled. > Yes, in order to use DC3CO on PSR2 with Selective Fetch / manual tracking, we need to have a proper sequence for DC3CO entry/exit. but the current DE / DMC firmware's DC3CO exit sequence does not work correctly on PSR2 with Selective Fetch / manual tracking. when I got the proper sequence, I'll update it as soon as possible. > Br, > Anshuman Gupta. > > + if (crtc_state->enable_psr2_sel_fetch) > > + return; > > + > > if (!(dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO)) > > return; > > > > -- > > 2.30.0 > _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
