On Tue, Feb 09, 2021 at 04:28:28PM -0500, Lyude Paul wrote: > Since Intel has introduced the gen9_bc platform, a combination of > Tigerpoint PCHs and CML CPUs, let's recognize such platforms as valid and > avoid WARNing on them. > > Changes since v4: > * Split this into it's own patch - vsyrjala > > Cc: Matt Roper <matthew.d.roper@xxxxxxxxx> > Cc: Jani Nikula <jani.nikula@xxxxxxxxxxxxxxx> > Cc: Ville Syrjala <ville.syrjala@xxxxxxxxxxxxxxx> > [originally from Tejas's work] > Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@xxxxxxxxx> > Signed-off-by: Lyude Paul <lyude@xxxxxxxxxx> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx> > --- > drivers/gpu/drm/i915/intel_pch.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_pch.c b/drivers/gpu/drm/i915/intel_pch.c > index 4813207fc053..7476f0e063c6 100644 > --- a/drivers/gpu/drm/i915/intel_pch.c > +++ b/drivers/gpu/drm/i915/intel_pch.c > @@ -121,7 +121,8 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id) > case INTEL_PCH_TGP2_DEVICE_ID_TYPE: > drm_dbg_kms(&dev_priv->drm, "Found Tiger Lake LP PCH\n"); > drm_WARN_ON(&dev_priv->drm, !IS_TIGERLAKE(dev_priv) && > - !IS_ROCKETLAKE(dev_priv)); > + !IS_ROCKETLAKE(dev_priv) && > + !IS_GEN9_BC(dev_priv)); > return PCH_TGP; > case INTEL_PCH_JSP_DEVICE_ID_TYPE: > case INTEL_PCH_JSP2_DEVICE_ID_TYPE: > -- > 2.29.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
