On Mon, 08 Feb 2021, Jani Nikula <jani.nikula@xxxxxxxxxxxxxxx> wrote: > Subject prefix: drm/i915: > > On Mon, 08 Feb 2021, Ankit Nautiyal <ankit.k.nautiyal@xxxxxxxxx> wrote: >> Legacy LSPCON chip from MCA and Parade is only used for platforms >> between GEN9 and GEN10. Fixing the HAS_LSPCON macro to reflect the same. >> >> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@xxxxxxxxx> > > I cringe at the VBT having the bit set anyway, but > > Acked-by: Jani Nikula <jani.nikula@xxxxxxxxx> And pushed, thanks for the patch. Fixed the subject while applying. BR, Jani. > >> --- >> drivers/gpu/drm/i915/i915_drv.h | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h >> index 4fc9a8691873..fd04fc434ca6 100644 >> --- a/drivers/gpu/drm/i915/i915_drv.h >> +++ b/drivers/gpu/drm/i915/i915_drv.h >> @@ -1763,7 +1763,7 @@ tgl_stepping_get(struct drm_i915_private *dev_priv) >> >> #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch) >> >> -#define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9) >> +#define HAS_LSPCON(dev_priv) (IS_GEN_RANGE(dev_priv, 9, 10)) >> >> /* DPF == dynamic parity feature */ >> #define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf) -- Jani Nikula, Intel Open Source Graphics Center _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
