While the HW may support preemption, whether or not the scheduler
enforces preemption by forcibly resetting the current context is
ultimately up to the scheduler.
Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@xxxxxxxxx>
---
drivers/gpu/drm/i915/gt/intel_engine.h | 7 ++-----
drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c | 4 ++--
drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 4 +++-
drivers/gpu/drm/i915/i915_scheduler_types.h | 9 +++++++++
4 files changed, 16 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h
index 5d3bcbfe8f6e..e4f390bba009 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -244,12 +244,9 @@ static inline bool intel_engine_uses_guc(const struct intel_engine_cs *engine)
}
static inline bool
-intel_engine_has_preempt_reset(const struct intel_engine_cs *engine)
+intel_engine_has_preempt_reset(struct intel_engine_cs *engine)
{
- if (!IS_ACTIVE(CONFIG_DRM_I915_PREEMPT_TIMEOUT))
- return false;
-
- return intel_engine_has_preemption(engine);
+ return i915_sched_has_preempt_reset(intel_engine_get_scheduler(engine));
}
static inline bool
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
index 209a477af412..5ed263f36f93 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
@@ -22,11 +22,11 @@
#define HEARTBEAT_COMPLETION 50u /* milliseconds */
-static long completion_timeout(const struct intel_engine_cs *engine)
+static long completion_timeout(struct intel_engine_cs *engine)
{
long timeout = HEARTBEAT_COMPLETION;
- if (intel_engine_has_preempt_reset(engine))
+ if (i915_sched_has_preempt_reset(intel_engine_get_scheduler(engine)))
timeout += READ_ONCE(engine->props.preempt_timeout_ms);
return msecs_to_jiffies(timeout);
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 0a93386ad15f..78fda9b4f626 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -2963,8 +2963,10 @@ static void init_execlists(struct intel_engine_cs *engine)
intel_engine_has_preemption(engine))
__set_bit(I915_SCHED_TIMESLICE_BIT, &engine->sched.flags);
- if (intel_engine_has_preemption(engine))
+ if (intel_engine_has_preemption(engine)) {
__set_bit(I915_SCHED_BUSYWAIT_BIT, &engine->sched.flags);
+ __set_bit(I915_SCHED_PREEMPT_RESET_BIT, &engine->sched.flags);
+ }
timer_setup(&engine->execlists.timer, execlists_timeslice, 0);
timer_setup(&engine->execlists.preempt, execlists_preempt, 0);
diff --git a/drivers/gpu/drm/i915/i915_scheduler_types.h b/drivers/gpu/drm/i915/i915_scheduler_types.h
index 3aaf5b40b801..5ca2dc1b4fb5 100644
--- a/drivers/gpu/drm/i915/i915_scheduler_types.h
+++ b/drivers/gpu/drm/i915/i915_scheduler_types.h
@@ -23,6 +23,7 @@ enum {
I915_SCHED_ACTIVE_BIT, /* can reorder the request flow */
I915_SCHED_PRIORITY_BIT, /* priority sorting of queue */
I915_SCHED_TIMESLICE_BIT, /* multitasking for long workloads */
+ I915_SCHED_PREEMPT_RESET_BIT, /* reset if preemption times out */
I915_SCHED_BUSYWAIT_BIT, /* preempt-to-busy */
};
@@ -256,4 +257,12 @@ static inline bool i915_sched_use_busywait(const struct i915_sched *se)
return test_bit(I915_SCHED_BUSYWAIT_BIT, &se->flags);
}
+static inline bool i915_sched_has_preempt_reset(const struct i915_sched *se)
+{
+ if (!IS_ACTIVE(CONFIG_DRM_I915_PREEMPT_TIMEOUT))
+ return false;
+
+ return test_bit(I915_SCHED_PREEMPT_RESET_BIT, &se->flags);
+}
+
#endif /* _I915_SCHEDULER_TYPES_H_ */
--
2.20.1
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