From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> The DDI clock routing programming is riddled with shared registers, forcing us to do a lot of RMW. Switch over to intel_de_rmw() to make that a bit less obnoxious. Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> --- drivers/gpu/drm/i915/display/intel_ddi.c | 78 +++++++++--------------- 1 file changed, 28 insertions(+), 50 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index aac85e86d776..7137929f58bd 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -3164,7 +3164,6 @@ static void dg1_ddi_enable_clock(struct intel_encoder *encoder, struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_shared_dpll *pll = crtc_state->shared_dpll; enum phy phy = intel_port_to_phy(dev_priv, encoder->port); - u32 val; /* * If we fail this, something went very wrong: first 2 PLLs should be @@ -3177,17 +3176,12 @@ static void dg1_ddi_enable_clock(struct intel_encoder *encoder, mutex_lock(&dev_priv->dpll.lock); - val = intel_de_read(dev_priv, DG1_DPCLKA_CFGCR0(phy)); - drm_WARN_ON(&dev_priv->drm, - (val & DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)) == 0); + intel_de_rmw(dev_priv, DG1_DPCLKA_CFGCR0(phy), + DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), + DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy)); - val &= ~DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); - val |= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); - intel_de_write(dev_priv, DG1_DPCLKA_CFGCR0(phy), val); - intel_de_posting_read(dev_priv, DG1_DPCLKA_CFGCR0(phy)); - - val &= ~DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); - intel_de_write(dev_priv, DG1_DPCLKA_CFGCR0(phy), val); + intel_de_rmw(dev_priv, DG1_DPCLKA_CFGCR0(phy), + DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy), 0); mutex_unlock(&dev_priv->dpll.lock); } @@ -3199,8 +3193,8 @@ static void dg1_ddi_disable_clock(struct intel_encoder *encoder) mutex_lock(&dev_priv->dpll.lock); - intel_de_rmw(dev_priv, DG1_DPCLKA_CFGCR0(phy), 0, - DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); + intel_de_rmw(dev_priv, DG1_DPCLKA_CFGCR0(phy), + 0, DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); mutex_unlock(&dev_priv->dpll.lock); } @@ -3212,14 +3206,9 @@ static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder, struct intel_shared_dpll *pll = crtc_state->shared_dpll; enum phy phy = intel_port_to_phy(dev_priv, encoder->port); i915_reg_t reg = icl_dpclka_cfgcr0_reg(dev_priv, phy); - u32 val; mutex_lock(&dev_priv->dpll.lock); - val = intel_de_read(dev_priv, reg); - drm_WARN_ON(&dev_priv->drm, - (val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0); - /* * Even though this register references DDIs, note that we * want to pass the PHY rather than the port (DDI). For @@ -3230,13 +3219,12 @@ static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder, * Clock Select chooses the PLL for both DDIA and DDID and * drives port A in all cases." */ - val &= ~icl_dpclka_cfgcr0_clk_sel_mask(dev_priv, phy); - val |= icl_dpclka_cfgcr0_clk_sel(dev_priv, pll->info->id, phy); - intel_de_write(dev_priv, reg, val); - intel_de_posting_read(dev_priv, reg); + intel_de_rmw(dev_priv, reg, + icl_dpclka_cfgcr0_clk_sel_mask(dev_priv, phy), + icl_dpclka_cfgcr0_clk_sel(dev_priv, pll->info->id, phy)); - val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, phy); - intel_de_write(dev_priv, reg, val); + intel_de_rmw(dev_priv, reg, + icl_dpclka_cfgcr0_clk_off(dev_priv, phy), 0); mutex_unlock(&dev_priv->dpll.lock); } @@ -3246,14 +3234,11 @@ static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder) struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); enum phy phy = intel_port_to_phy(dev_priv, encoder->port); i915_reg_t reg = icl_dpclka_cfgcr0_reg(dev_priv, phy); - u32 val; mutex_lock(&dev_priv->dpll.lock); - val = intel_de_read(dev_priv, reg); - val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy); - - intel_de_write(dev_priv, reg, val); + intel_de_rmw(dev_priv, reg, + 0, icl_dpclka_cfgcr0_clk_off(dev_priv, phy)); mutex_unlock(&dev_priv->dpll.lock); } @@ -3453,25 +3438,22 @@ static void cnl_ddi_enable_clock(struct intel_encoder *encoder, struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); const struct intel_shared_dpll *pll = crtc_state->shared_dpll; enum port port = encoder->port; - u32 val; if (drm_WARN_ON(&dev_priv->drm, !pll)) return; mutex_lock(&dev_priv->dpll.lock); - val = intel_de_read(dev_priv, DPCLKA_CFGCR0); - val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port); - val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port); - intel_de_write(dev_priv, DPCLKA_CFGCR0, val); + intel_de_rmw(dev_priv, DPCLKA_CFGCR0, + DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port), + DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port)); /* * "This step and the step before must be * done with separate register writes." */ - val = intel_de_read(dev_priv, DPCLKA_CFGCR0); - val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port); - intel_de_write(dev_priv, DPCLKA_CFGCR0, val); + intel_de_rmw(dev_priv, DPCLKA_CFGCR0, + DPCLKA_CFGCR0_DDI_CLK_OFF(port), 0); mutex_unlock(&dev_priv->dpll.lock); } @@ -3481,8 +3463,8 @@ static void cnl_ddi_disable_clock(struct intel_encoder *encoder) struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); enum port port = encoder->port; - intel_de_write(dev_priv, DPCLKA_CFGCR0, - intel_de_read(dev_priv, DPCLKA_CFGCR0) | DPCLKA_CFGCR0_DDI_CLK_OFF(port)); + intel_de_rmw(dev_priv, DPCLKA_CFGCR0, + 0, DPCLKA_CFGCR0_DDI_CLK_OFF(port)); } static void skl_ddi_enable_clock(struct intel_encoder *encoder, @@ -3491,21 +3473,17 @@ static void skl_ddi_enable_clock(struct intel_encoder *encoder, struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); const struct intel_shared_dpll *pll = crtc_state->shared_dpll; enum port port = encoder->port; - u32 val; if (drm_WARN_ON(&dev_priv->drm, !pll)) return; mutex_lock(&dev_priv->dpll.lock); - val = intel_de_read(dev_priv, DPLL_CTRL2); - - val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) | - DPLL_CTRL2_DDI_CLK_SEL_MASK(port)); - val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) | - DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); - - intel_de_write(dev_priv, DPLL_CTRL2, val); + intel_de_rmw(dev_priv, DPLL_CTRL2, + DPLL_CTRL2_DDI_CLK_OFF(port) | + DPLL_CTRL2_DDI_CLK_SEL_MASK(port), + DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) | + DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); mutex_unlock(&dev_priv->dpll.lock); } @@ -3515,8 +3493,8 @@ static void skl_ddi_disable_clock(struct intel_encoder *encoder) struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); enum port port = encoder->port; - intel_de_write(dev_priv, DPLL_CTRL2, - intel_de_read(dev_priv, DPLL_CTRL2) | DPLL_CTRL2_DDI_CLK_OFF(port)); + intel_de_rmw(dev_priv, DPLL_CTRL2, + 0, DPLL_CTRL2_DDI_CLK_OFF(port)); } static void hsw_ddi_enable_clock(struct intel_encoder *encoder, -- 2.26.2 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
