On Fri, Jan 29, 2021 at 07:22:49PM +0200, Imre Deak wrote:
> On Thu, Jan 28, 2021 at 05:59:47PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> >
> > The documented programming sequence indicates the correct point
> > for the vswing programming is just before we enable the DDI.
> > Make it so.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> > ---
> > drivers/gpu/drm/i915/display/intel_ddi.c | 30 ++++++++++++------------
> > 1 file changed, 15 insertions(+), 15 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index 8fbeb8c24efb..efcdf5499903 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -3893,7 +3893,6 @@ static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state,
> > struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> > struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
> > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > - int level = intel_ddi_hdmi_level(encoder, crtc_state);
> >
> > intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
> > intel_ddi_clk_select(encoder, crtc_state);
> > @@ -3904,20 +3903,6 @@ static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state,
> >
> > icl_program_mg_dp_mode(dig_port, crtc_state);
> >
> > - if (INTEL_GEN(dev_priv) >= 12)
> > - tgl_ddi_vswing_sequence(encoder, crtc_state, level);
> > - else if (INTEL_GEN(dev_priv) == 11)
> > - icl_ddi_vswing_sequence(encoder, crtc_state, level);
> > - else if (IS_CANNONLAKE(dev_priv))
> > - cnl_ddi_vswing_sequence(encoder, crtc_state, level);
> > - else if (IS_GEN9_LP(dev_priv))
> > - bxt_ddi_vswing_sequence(encoder, crtc_state, level);
> > - else
> > - intel_prepare_hdmi_ddi_buffers(encoder, level);
> > -
> > - if (IS_GEN9_BC(dev_priv))
> > - skl_ddi_set_iboost(encoder, crtc_state, level);
> > -
> > intel_ddi_enable_pipe_clock(encoder, crtc_state);
> >
> > dig_port->set_infoframes(encoder,
> > @@ -4293,6 +4278,7 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
> > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> > struct drm_connector *connector = conn_state->connector;
> > + int level = intel_ddi_hdmi_level(encoder, crtc_state);
> > enum port port = encoder->port;
> >
> > if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
> > @@ -4302,6 +4288,20 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
> > "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n",
> > connector->base.id, connector->name);
> >
> > + if (INTEL_GEN(dev_priv) >= 12)
> > + tgl_ddi_vswing_sequence(encoder, crtc_state, level);
> > + else if (INTEL_GEN(dev_priv) == 11)
> > + icl_ddi_vswing_sequence(encoder, crtc_state, level);
> > + else if (IS_CANNONLAKE(dev_priv))
> > + cnl_ddi_vswing_sequence(encoder, crtc_state, level);
> > + else if (IS_GEN9_LP(dev_priv))
> > + bxt_ddi_vswing_sequence(encoder, crtc_state, level);
> > + else
> > + intel_prepare_hdmi_ddi_buffers(encoder, level);
>
> It's not specified where to do this on HSW, but I assume it matches BDW:
Should be fine. All we get on HSW is
"DDI_BUF_TRANS: ...
Restriction : These registers must be programmed with valid values
prior to enabling DDI_BUF_CTL."
> Reviewed-by: Imre Deak <imre.deak@xxxxxxxxx>
>
> > +
> > + if (IS_GEN9_BC(dev_priv))
> > + skl_ddi_set_iboost(encoder, crtc_state, level);
> > +
> > /* Display WA #1143: skl,kbl,cfl */
> > if (IS_GEN9_BC(dev_priv)) {
> > /*
> > --
> > 2.26.2
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
