From: CQ Tang <cq.tang@xxxxxxxxx>
The lmem region needs to remove the stolen part, which should just be a
case of snipping it off the end.
Signed-off-by: CQ Tang <cq.tang@xxxxxxxxx>
Signed-off-by: Matthew Auld <matthew.auld@xxxxxxxxx>
---
drivers/gpu/drm/i915/gt/intel_region_lmem.c | 13 +++++++++----
drivers/gpu/drm/i915/i915_reg.h | 2 ++
2 files changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
index b3d1d0abb956..71bb38706dbf 100644
--- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
@@ -146,20 +146,24 @@ intel_gt_setup_fake_lmem(struct intel_gt *gt)
static struct intel_memory_region *setup_lmem(struct intel_gt *gt)
{
struct drm_i915_private *i915 = gt->i915;
+ struct intel_uncore *uncore = gt->uncore;
struct pci_dev *pdev = i915->drm.pdev;
struct intel_memory_region *mem;
resource_size_t io_start;
- resource_size_t size;
+ resource_size_t lmem_size;
if (!IS_DGFX(i915))
return ERR_PTR(-ENODEV);
+ /* Stolen starts from GSMBASE on DG1 */
+ lmem_size = intel_uncore_read64(uncore, GEN12_GSMBASE);
+
io_start = pci_resource_start(pdev, 2);
- size = pci_resource_len(pdev, 2);
+ GEM_BUG_ON(lmem_size > pci_resource_len(pdev, 2));
mem = intel_memory_region_create(i915,
0,
- size,
+ lmem_size,
I915_GTT_PAGE_SIZE_4K,
io_start,
&intel_region_lmem_ops);
@@ -167,7 +171,8 @@ static struct intel_memory_region *setup_lmem(struct intel_gt *gt)
drm_dbg(&i915->drm, "Local memory: %pR\n", &mem->region);
drm_dbg(&i915->drm, "Local memory IO start: %pa\n",
&mem->io_start);
- drm_info(&i915->drm, "Local memory available: %pa\n", &size);
+ drm_info(&i915->drm, "Local memory available: %pa\n",
+ &lmem_size);
}
return mem;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index aa872446337b..b39b46a974b5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -12160,6 +12160,8 @@ enum skl_power_gate {
#define GEN12_GLOBAL_MOCS(i) _MMIO(0x4000 + (i) * 4) /* Global MOCS regs */
+#define GEN12_GSMBASE _MMIO(0x108100)
+
/* gamt regs */
#define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
#define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW 0x67F1427F /* max/min for LRA1/2 */
--
2.26.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
