✓ Fi.CI.BAT: success for series starting with [CI,v6] drm/i915/display/vrr: Create VRR file and add VRR capability check (rev2)

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Title: Project List - Patchwork
Patch Details
Series:series starting with [CI,v6] drm/i915/display/vrr: Create VRR file and add VRR capability check (rev2)
URL:https://patchwork.freedesktop.org/series/86200/
State:success
Details:https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19492/index.html

CI Bug Log - changes from CI_DRM_9680 -> Patchwork_19492

Summary

SUCCESS

No regressions found.

External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19492/index.html

Possible new issues

Here are the unknown changes that may have been introduced in Patchwork_19492:

IGT changes

Suppressed

The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.

New tests

New tests have been introduced between CI_DRM_9680 and Patchwork_19492:

New IGT tests (1)

Known issues

Here are the changes found in Patchwork_19492 that come from known issues:

IGT changes

Issues hit

Possible fixes

{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).

Participating hosts (39 -> 36)

Additional (1): fi-rkl-11500t
Missing (4): fi-ctg-p8600 fi-jsl-1 fi-ilk-m540 fi-hsw-4200u

Build changes

CI-20190529: 20190529
CI_DRM_9680: 9e03236ed9687144929d42404341384cc1e501b7 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5971: abef2b7d6ff30f3b948b3e5d39653debb73083f3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19492: e6f1e331f9957c9eb7662c26db3ba44a53964bb8 @ git://anongit.freedesktop.org/gfx-ci/linux

== Linux commits ==

e6f1e331f995 drm/i915: Fix vblank evasion with vrr
58b14daa2aa2 drm/i915: Fix vblank timestamps with VRR
e4b1a4ab29b6 drm/i915: Add vrr state dump
7422bf611bda drm/i915/display: Helpers for VRR vblank min and max start
fccf4001ed51 drm/i915/display: Add HW state readout for VRR
fd521ea70cf2 drm/i915/display/vrr: Set IGNORE_MSA_PAR state in DP Sink
f58744d7fa53 drm/i915/display/vrr: Disable VRR in modeset disable path
9afbc5d3d2c7 drm/i915/display/vrr: Send VRR push to flip the frame
7fafcbdaedbf drm/i915/display/vrr: Configure and enable VRR in modeset enable
9b63d63f6613 drm/i915: Rename VRR_CTL reg fields
48ea525edcf8 drm/i915/display: VRR + DRRS cannot be enabled together
348ab07c113b drm/i915/display/dp: Do not enable PSR if VRR is enabled
d042de272b5c drm/i915/display/dp: Compute VRR state in atomic_check
e09f65af8a5b drm/i915: Extract intel_crtc_scanlines_since_frame_timestamp()
b6d69ba3c3f2 drm/i915: Extract intel_mode_vblank_start()
215e991209ec drm/i915: Store framestart_delay in dev_priv
f52206f4d61d drm/i915/display/dp: Attach and set drm connector VRR property
62a318f6e2ec drm/i915/display/vrr: Create VRR file and add VRR capability check

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