On Fri, Dec 04, 2020 at 05:08:33PM -0800, Aditya Swarup wrote:
> ADL-S requires TC pins to set up ddc for Combo PHY B, C, D and E.
> Combo PHY A still uses the old ddc pin mapping.
>
> From VBT, ddc pin info suggests the following mapping:
> VBT DRIVER
> DDI B->ddc_pin=2 should translate to PORT_D->0x9
> DDI C->ddc_pin=3 should translate to PORT_E->0xa
> DDI D->ddc_pin=4 should translate to PORT_F->0xb
> DDI E->ddc_pin=5 should translate to PORT_G->0xc
>
> Adding pin map to facilitate this translation as we cannot use existing
> icl ddc pin map due to conflict with DDI B and DDI C info.
>
> Bspec:20124
>
> v2: Replace IS_ALDERLAKE_S() with HAS_PCH_ADP() as the pin map pairing
> depends on the PCH being used rather than the platform.(mdroper)
>
> Cc: Jani Nikula <jani.nikula@xxxxxxxxx>
> Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> Cc: Imre Deak <imre.deak@xxxxxxxxx>
> Cc: Matt Roper <matthew.d.roper@xxxxxxxxx>
> Cc: Lucas De Marchi <lucas.demarchi@xxxxxxxxx>
> Signed-off-by: Aditya Swarup <aditya.swarup@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_bios.c | 13 +++++++++++-
> drivers/gpu/drm/i915/display/intel_hdmi.c | 20 ++++++++++++++++++-
> drivers/gpu/drm/i915/display/intel_vbt_defs.h | 4 ++++
> 3 files changed, 35 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
> index 4cc949b228f2..9dc67c03ffc0 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -1623,12 +1623,23 @@ static const u8 icp_ddc_pin_map[] = {
> [TGL_DDC_BUS_PORT_6] = GMBUS_PIN_14_TC6_TGP,
> };
>
> +static const u8 adls_ddc_pin_map[] = {
> + [ICL_DDC_BUS_DDI_A] = GMBUS_PIN_1_BXT,
> + [ADLS_DDC_BUS_PORT_TC1] = GMBUS_PIN_9_TC1_ICP,
> + [ADLS_DDC_BUS_PORT_TC2] = GMBUS_PIN_10_TC2_ICP,
> + [ADLS_DDC_BUS_PORT_TC3] = GMBUS_PIN_11_TC3_ICP,
> + [ADLS_DDC_BUS_PORT_TC4] = GMBUS_PIN_12_TC4_ICP,
> +};
Can't we use icp_ddc_pin_map[] since it's a superset of this? The ICP
table has some extra entries that we'll never map through, but that's
true for other platforms as well. E.g., ICP itself can never have a
DDI_C or TC5/TC6, but it doesn't hurt anything to have those outputs as
extra entries in the table that never get looked up.
> +
> static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin)
> {
> const u8 *ddc_pin_map;
> int n_entries;
>
> - if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) {
> + if (HAS_PCH_ADP(dev_priv)) {
> + ddc_pin_map = adls_ddc_pin_map;
> + n_entries = ARRAY_SIZE(adls_ddc_pin_map);
> + } else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) {
> return vbt_pin;
> } else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) {
> ddc_pin_map = icp_ddc_pin_map;
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index e10fdb369daa..060a13b63aa9 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -3135,6 +3135,22 @@ static u8 dg1_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
> return intel_port_to_phy(dev_priv, port) + 1;
> }
>
> +static u8 adls_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
> +{
> + enum phy phy = intel_port_to_phy(dev_priv, port);
> +
> + WARN_ON(port == PORT_B || port == PORT_C);
> +
> + /*
> + * Pin mapping for ADL-S requires TC pins for all combo phy outputs
> + * except first combo output.
> + */
> + if (IS_ALDERLAKE_S(dev_priv) && phy >= PHY_B)
The IS_ADLS test here is redundant since we only call this function on
ADL-S, right?
> + return GMBUS_PIN_9_TC1_ICP + phy - PHY_B;
> +
> + return GMBUS_PIN_1_BXT + phy;
There's only one possible output that can get to this return
(PORT_A/PHY_A), so the generic "+ phy" seems unnecessary.
Actually it might more more sensible to make PHY_A the special case we
test for in the 'if' condition and then make the PHY_B+ case the
function's regular return.
> +}
> +
> static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
> enum port port)
> {
> @@ -3172,7 +3188,9 @@ static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder)
> return ddc_pin;
> }
>
> - if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
> + if (IS_ALDERLAKE_S(dev_priv))
This should probably be a PCH check instead of a platform check too.
Matt
> + ddc_pin = adls_port_to_ddc_pin(dev_priv, port);
> + else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
> ddc_pin = dg1_port_to_ddc_pin(dev_priv, port);
> else if (IS_ROCKETLAKE(dev_priv))
> ddc_pin = rkl_port_to_ddc_pin(dev_priv, port);
> diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> index 49b4b5fca941..32d1b4f05760 100644
> --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> @@ -325,6 +325,10 @@ enum vbt_gmbus_ddi {
> ICL_DDC_BUS_PORT_4,
> TGL_DDC_BUS_PORT_5,
> TGL_DDC_BUS_PORT_6,
> + ADLS_DDC_BUS_PORT_TC1 = 0x2,
> + ADLS_DDC_BUS_PORT_TC2,
> + ADLS_DDC_BUS_PORT_TC3,
> + ADLS_DDC_BUS_PORT_TC4
> };
>
> #define DP_AUX_A 0x40
> --
> 2.27.0
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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