On Thu, Mar 07, 2013 at 11:43:14AM +0200, Ville Syrj?l? wrote: > On Wed, Mar 06, 2013 at 08:03:15PM -0300, Paulo Zanoni wrote: > > From: Paulo Zanoni <paulo.r.zanoni at intel.com> > > > > I couldn't find any evidence that this register exists on Gen2+. On > > Gen 2/3/4 documents this register is listed as reserved and read-only. > > On the newer Gens this register is not even documented. > > DSPPOS goes hand in hand with DSPSIZE. IIRC DSPA never had the > windowing capability, but DSPB and DSPC on older gens had it. Indeed Ville's right here, gen2/3 have this on sprite B/C (you could move those things around back then to different pipes ...). So I think we want a gen <= 3 check here (gen4+ lost this apparently with the fixed pipe->plane mapping). -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch
