On Wed, Mar 06, 2013 at 08:03:15PM -0300, Paulo Zanoni wrote: > From: Paulo Zanoni <paulo.r.zanoni at intel.com> > > I couldn't find any evidence that this register exists on Gen2+. On > Gen 2/3/4 documents this register is listed as reserved and read-only. > On the newer Gens this register is not even documented. > > Also all we do with this register is: > - Write 0 to it on i9xx_crtc_mode_set > - Save/restore its value on the UMS code > - Read it on intel_display_capture_error_state > > This commit fixes "unclaimed register" messages when there's a GPU > hang on Haswell. > > Signed-off-by: Paulo Zanoni <paulo.r.zanoni at intel.com> Reviewed-by: Ben Widawsky <ben at bwidawsk.net> [snip] -- Ben Widawsky, Intel Open Source Technology Center
