Hi,
On Mon, Dec 21, 2020 at 04:07:58AM +0000, Matthew Wilcox wrote:
>
> At boot,
>
> [ 2.787995] [drm:lspcon_init [i915]] *ERROR* Failed to probe lspcon
> [ 2.788001] i915 0000:00:02.0: [drm] *ERROR* LSPCON init failed on port E
> [ 2.790752] ------------[ cut here ]------------
> [ 2.790753] Missing case (clock == 539440)
> [ 2.790790] WARNING: CPU: 0 PID: 159 at drivers/gpu/drm/i915/display/intel_dpll_mgr.c:2967 icl_get_dplls+0x53a/0xa50 [i915]
the above warn looks to be due to a missing workaround fixed by
commit 0e2497e334de42dbaaee8e325241b5b5b34ede7e
Author: Imre Deak <imre.deak@xxxxxxxxx>
Date: Sat Oct 3 03:18:46 2020 +0300
drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock
in drm-tip. Could you give it a try?
> In drivers/gpu/drm/i915/display/intel_dpll_mgr.c, I see an entry for 540,000.
> Presumbly, this clock was supposed to be rounded up to that somewhere.
> This is an HP Spectre x360 using the internal display. Here's the EDID
> in case that's useful:
>
> $ edid-decode /sys/class/drm/card0-eDP-1/edid
> edid-decode (hex):
>
> 00 ff ff ff ff ff ff 00 4c 83 49 41 00 00 00 00
> 13 1d 01 04 b5 1d 11 78 02 38 d1 ae 51 3b b8 23
> 0b 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01
> 01 01 01 01 01 01 b9 d5 00 40 f1 70 20 80 30 20
> 88 00 26 a5 10 00 00 1b b9 d5 00 40 f1 70 20 80
> 30 20 88 00 26 a5 10 00 00 1b 00 00 00 0f 00 ff
> 09 3c ff 09 3c 2c 80 00 00 00 00 00 00 00 00 10
> 00 00 01 00 00 00 00 00 00 00 00 00 00 00 01 af
>
> 02 03 0f 00 e3 05 80 00 e6 06 05 01 73 6d 07 00
> 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ab
>
> ----------------
>
> EDID version: 1.4
> Manufacturer: SDC Model 16713 Serial Number 0
> Made in week 19 of 2019
> Digital display
> 10 bits per primary color channel
> DisplayPort interface
> Maximum image size: 29 cm x 17 cm
> Gamma: 2.20
> Supported color formats: RGB 4:4:4
> First detailed timing includes the native pixel format and preferred refresh rate
> Color Characteristics
> Red: 0.6796, 0.3193
> Green: 0.2324, 0.7187
> Blue: 0.1396, 0.0439
> White: 0.3125, 0.3291
> Established Timings I & II: none
> Standard Timings: none
> Detailed mode: Clock 547.130 MHz, 294 mm x 165 mm
> 3840 3888 3920 4160 ( 48 32 240)
> 2160 2168 2176 2192 ( 8 8 16)
> +hsync -vsync
> VertFreq: 60.001 Hz, HorFreq: 131.522 kHz
> Detailed mode: Clock 547.130 MHz, 294 mm x 165 mm
> 3840 3888 3920 4160 ( 48 32 240)
> 2160 2168 2176 2192 ( 8 8 16)
> +hsync -vsync
> VertFreq: 60.001 Hz, HorFreq: 131.522 kHz
> Manufacturer-Specified Display Descriptor (0x0f): 00 0f 00 ff 09 3c ff 09 3c 2c 80 00 00 00 00 00 .....<..<,......
> Dummy Descriptor
> Has 1 extension block
> Checksum: 0xaf
>
> ----------------
>
> CTA-861 Extension Block Revision 3
> 0 native detailed modes
> 11 bytes of CTA data blocks
> Extended tag: Colorimetry Data Block
> BT2020RGB
> Extended tag: HDR Static Metadata Data Block
> Electro optical transfer functions:
> Traditional gamma - SDR luminance range
> SMPTE ST2084
> Supported static metadata descriptors:
> Static metadata type 1
> Desired content max luminance: 115 (603.666 cd/m^2)
> Desired content max frame-average luminance: 109 (530.095 cd/m^2)
> Desired content min luminance: 7 (0.005 cd/m^2)
> Checksum: 0xab
>
>
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