Quoting Huang, Sean Z (2020-12-10 07:24:16) > Set the KCR init during the boot time, which is > required by hardware, to allow us doing further > protection operation such as sending commands to > GPU or TEE. > > Signed-off-by: Huang, Sean Z <sean.z.huang@xxxxxxxxx> > --- > drivers/gpu/drm/i915/pxp/intel_pxp.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c > index ba43b2c923c7..c4815950567d 100644 > --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c > +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c > @@ -6,6 +6,12 @@ > #include "intel_pxp.h" > #include "intel_pxp_context.h" > > +/* KCR register definitions */ > +#define KCR_INIT _MMIO(0x320f0) > +#define KCR_INIT_MASK_SHIFT (16) > +/* Setting KCR Init bit is required after system boot */ > +#define KCR_INIT_ALLOW_DISPLAY_ME_WRITES (BIT(14) | (BIT(14) << KCR_INIT_MASK_SHIFT)) That's a regular masked register. #define KCR_INIT_ALLOW_DISPLAY_ME_WRITES REG_BIT(14) intel_uncore_write(gt->uncore, KCR_INIT, _MASKED_ENABLE(KCR_INIT_ALLOW_DISPLAY_ME_WRITES)); > + > int intel_pxp_init(struct intel_pxp *pxp) > { > struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp); > @@ -16,6 +22,8 @@ int intel_pxp_init(struct intel_pxp *pxp) > > intel_pxp_ctx_init(&pxp->ctx); > > + intel_uncore_write(gt->uncore, KCR_INIT, KCR_INIT_ALLOW_DISPLAY_ME_WRITES); > + > drm_info(>->i915->drm, "Protected Xe Path (PXP) protected content support initialized\n"); > > return 0; > -- > 2.17.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx