Quoting Lucas De Marchi (2020-12-09 04:52:46) > Document what a masked register is according to bspec so we avoid > developers using the wrong functions to implement WAs. > > Signed-off-by: Lucas De Marchi <lucas.demarchi@xxxxxxxxx> > --- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 11 +++++++++++ > 1 file changed, 11 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index fec099f6ae76..b5339a36d256 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -217,6 +217,17 @@ wa_write_clr(struct i915_wa_list *wal, i915_reg_t reg, u32 clr) > wa_write_clr_set(wal, reg, clr, 0); > } > > +/* > + * WA operations on "masked register". A masked register has the upper 16 bits > + * documented as "masked" in b-spec. Its purpose is to allow writing to just a > + * portion of the register without a rmw: you simply write in the upper 16 bits > + * the mask of bits you are going to modify. > + * > + * The wa_masked_* family of functions already does the necessary operations to > + * calculate the mask based on the parameters passed, so user only has to > + * provide the lower 16 bits of that register. > + */ Reviewed-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
