On Tue, Dec 08, 2020 at 02:33:54PM +0200, Jani Nikula wrote: > The VBT fields match the DPCD data, so use the same helper. > > Cc: Manasi Navare <manasi.d.navare@xxxxxxxxx> > Cc: Vandita Kulkarni <vandita.kulkarni@xxxxxxxxx> > Signed-off-by: Jani Nikula <jani.nikula@xxxxxxxxx> Only for DSI so far right? In that case looks good Reviewed-by: Manasi Navare <manasi.d.navare@xxxxxxxxx> Manasi > --- > drivers/gpu/drm/i915/display/intel_bios.c | 11 +++-------- > 1 file changed, 3 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c > index 4cc949b228f2..06c3310446a2 100644 > --- a/drivers/gpu/drm/i915/display/intel_bios.c > +++ b/drivers/gpu/drm/i915/display/intel_bios.c > @@ -2555,16 +2555,11 @@ static void fill_dsc(struct intel_crtc_state *crtc_state, > crtc_state->dsc.slice_count); > > /* > - * FIXME: Use VBT rc_buffer_block_size and rc_buffer_size for the > - * implementation specific physical rate buffer size. Currently we use > - * the required rate buffer model size calculated in > - * drm_dsc_compute_rc_parameters() according to VESA DSC Annex E. > - * > * The VBT rc_buffer_block_size and rc_buffer_size definitions > - * correspond to DP 1.4 DPCD offsets 0x62 and 0x63. The DP DSC > - * implementation should also use the DPCD (or perhaps VBT for eDP) > - * provided value for the buffer size. > + * correspond to DP 1.4 DPCD offsets 0x62 and 0x63. > */ > + vdsc_cfg->rc_model_size = drm_dsc_dp_rc_buffer_size(dsc->rc_buffer_block_size, > + dsc->rc_buffer_size); > > /* FIXME: DSI spec says bpc + 1 for this one */ > vdsc_cfg->line_buf_depth = VBT_DSC_LINE_BUFFER_DEPTH(dsc->line_buffer_depth); > -- > 2.20.1 > _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
