Quoting Imre Deak (2020-12-01 20:50:21) > On Tue, Dec 01, 2020 at 12:34:35PM +0000, Chris Wilson wrote: > > There's also the matter of coherency. Is the object coherent for reads > > from the CPU? -- in most cases it will not be, but you should check > > obj->cache_coherency to see if the read requires a preceding > > cache_clflush_range() / drm_clflush_virt_range(). > > Ok, at this point for the TGL-only modifier, we could then just > warn_on(!bo_cache_coherent_for_read) due to HAS_LLC. Stupid question, is the same path required for dg1? That makes everything more difficult as the struct pages are gone. -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
