Quoting Matthew Auld (2020-11-27 12:04:40)
> From: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
>
> Cleanup intel_lrc.h by moving some of the residual common register
> definitions into intel_lrc_reg.h, prior to rebranding and splitting off
> the submission backends.
>
> v2: keep the SCHEDULE enum in the old file, since it is specific to the
> gvt usage of the execlists submission backend (John)
>
> Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@xxxxxxxxx> #v2
> Cc: John Harrison <John.C.Harrison@xxxxxxxxx>
> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_gt_irq.c | 1 +
> drivers/gpu/drm/i915/gt/intel_lrc.h | 39 -----------------------
> drivers/gpu/drm/i915/gt/intel_lrc_reg.h | 39 +++++++++++++++++++++++
> drivers/gpu/drm/i915/gvt/mmio_context.h | 2 ++
> 5 files changed, 43 insertions(+), 40 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index d4e988b2816a..02ea16b29c9f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -36,7 +36,7 @@
> #include "intel_gt.h"
> #include "intel_gt_requests.h"
> #include "intel_gt_pm.h"
> -#include "intel_lrc.h"
> +#include "intel_lrc_reg.h"
> #include "intel_reset.h"
> #include "intel_ring.h"
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> index 257063a57101..9830342aa6f4 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> @@ -11,6 +11,7 @@
> #include "intel_breadcrumbs.h"
> #include "intel_gt.h"
> #include "intel_gt_irq.h"
> +#include "intel_lrc_reg.h"
> #include "intel_uncore.h"
> #include "intel_rps.h"
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.h b/drivers/gpu/drm/i915/gt/intel_lrc.h
> index 802585a308e9..9116b46844a2 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.h
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.h
> @@ -34,45 +34,6 @@ struct i915_request;
> struct intel_context;
> struct intel_engine_cs;
>
> -/* Execlists regs */
> -#define RING_ELSP(base) _MMIO((base) + 0x230)
> -#define RING_EXECLIST_STATUS_LO(base) _MMIO((base) + 0x234)
> -#define RING_EXECLIST_STATUS_HI(base) _MMIO((base) + 0x234 + 4)
> -#define RING_CONTEXT_CONTROL(base) _MMIO((base) + 0x244)
> -#define CTX_CTRL_INHIBIT_SYN_CTX_SWITCH (1 << 3)
> -#define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT (1 << 0)
> -#define CTX_CTRL_RS_CTX_ENABLE (1 << 1)
> -#define CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT (1 << 2)
> -#define GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE (1 << 8)
> -#define RING_CONTEXT_STATUS_PTR(base) _MMIO((base) + 0x3a0)
> -#define RING_EXECLIST_SQ_CONTENTS(base) _MMIO((base) + 0x510)
> -#define RING_EXECLIST_CONTROL(base) _MMIO((base) + 0x550)
> -
> -#define EL_CTRL_LOAD (1 << 0)
> -
> -/* The docs specify that the write pointer wraps around after 5h, "After status
> - * is written out to the last available status QW at offset 5h, this pointer
> - * wraps to 0."
> - *
> - * Therefore, one must infer than even though there are 3 bits available, 6 and
> - * 7 appear to be * reserved.
> - */
> -#define GEN8_CSB_ENTRIES 6
> -#define GEN8_CSB_PTR_MASK 0x7
> -#define GEN8_CSB_READ_PTR_MASK (GEN8_CSB_PTR_MASK << 8)
> -#define GEN8_CSB_WRITE_PTR_MASK (GEN8_CSB_PTR_MASK << 0)
> -
> -#define GEN11_CSB_ENTRIES 12
> -#define GEN11_CSB_PTR_MASK 0xf
> -#define GEN11_CSB_READ_PTR_MASK (GEN11_CSB_PTR_MASK << 8)
> -#define GEN11_CSB_WRITE_PTR_MASK (GEN11_CSB_PTR_MASK << 0)
> -
> -#define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
> -#define MAX_GUC_CONTEXT_HW_ID (1 << 20) /* exclusive */
> -#define GEN11_MAX_CONTEXT_HW_ID (1<<11) /* exclusive */
> -/* in Gen12 ID 0x7FF is reserved to indicate idle */
> -#define GEN12_MAX_CONTEXT_HW_ID (GEN11_MAX_CONTEXT_HW_ID - 1)
> -
> enum {
> INTEL_CONTEXT_SCHEDULE_IN = 0,
> INTEL_CONTEXT_SCHEDULE_OUT,
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc_reg.h b/drivers/gpu/drm/i915/gt/intel_lrc_reg.h
> index 1b51f7b9a5c3..b2e03ce35599 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc_reg.h
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc_reg.h
> @@ -52,4 +52,43 @@
> #define GEN8_EXECLISTS_STATUS_BUF 0x370
> #define GEN11_EXECLISTS_STATUS_BUF2 0x3c0
>
> +/* Execlists regs */
> +#define RING_ELSP(base) _MMIO((base) + 0x230)
> +#define RING_EXECLIST_STATUS_LO(base) _MMIO((base) + 0x234)
> +#define RING_EXECLIST_STATUS_HI(base) _MMIO((base) + 0x234 + 4)
> +#define RING_CONTEXT_CONTROL(base) _MMIO((base) + 0x244)
> +#define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT REG_BIT(0)
> +#define CTX_CTRL_RS_CTX_ENABLE REG_BIT(1)
> +#define CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT REG_BIT(2)
> +#define CTX_CTRL_INHIBIT_SYN_CTX_SWITCH REG_BIT(3)
> +#define GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE REG_BIT(8)
> +#define RING_CONTEXT_STATUS_PTR(base) _MMIO((base) + 0x3a0)
> +#define RING_EXECLIST_SQ_CONTENTS(base) _MMIO((base) + 0x510)
> +#define RING_EXECLIST_CONTROL(base) _MMIO((base) + 0x550)
> +#define EL_CTRL_LOAD REG_BIT(0)
> +
> +/*
> + * The docs specify that the write pointer wraps around after 5h, "After status
> + * is written out to the last available status QW at offset 5h, this pointer
> + * wraps to 0."
> + *
> + * Therefore, one must infer than even though there are 3 bits available, 6 and
> + * 7 appear to be * reserved.
Stray '*'
That's a very weird statement. 6/7 simply do not exist, since the
ringbuffer doesn't have that many elements.
-Chris
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