> -----Original Message-----
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> Sent: Thursday, November 19, 2020 9:12 PM
> To: Shankar, Uma <uma.shankar@xxxxxxxxx>
> Cc: intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> Subject: Re: [v2 1/2] drm/i915/display/tgl: Disable FBC with PSR2
>
> On Thu, Nov 19, 2020 at 09:20:49PM +0530, Uma Shankar wrote:
> > There are some corner cases wrt underrun when we enable FBC with PSR2
> > on TGL. Recommendation from hardware is to keep this combination
> > disabled.
> >
> > Bspec: 50422 HSD: 14010260002
> >
> > v2: Added psr2 enabled check from crtc_state (Anshuman) Added Bspec
> > link and HSD referneces (Jose)
> >
> > Signed-off-by: Uma Shankar <uma.shankar@xxxxxxxxx>
> > ---
> > drivers/gpu/drm/i915/display/intel_fbc.c | 11 +++++++++++
> > 1 file changed, 11 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> > b/drivers/gpu/drm/i915/display/intel_fbc.c
> > index a5b072816a7b..c64ed1cd29b1 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > @@ -799,6 +799,17 @@ static bool intel_fbc_can_activate(struct intel_crtc
> *crtc)
> > struct intel_fbc *fbc = &dev_priv->fbc;
> > struct intel_fbc_state_cache *cache = &fbc->state_cache;
> >
> > + /*
> > + * Tigerlake is not supporting FBC with PSR2.
> > + * Recommendation is to keep this combination disabled
> > + * Bspec: 50422 HSD: 14010260002
> > + */
> > + if (crtc->config && crtc->config->has_psr2 &&
>
> Please don't add more crtc->config usages. After several years we've almost
> reached the point where we can finally remove it.
> I should porbably take a look at how much work would be required to at least
> make it always NULL on g4x+.
>
> The fbc state tracking is a total mess atm, but I think you can stuff this into
> intel_fbc_update_state_cache() and either just set cache->plane.visible=false
> (which is a bit of a lie but would work), or add a new thing into the
> params/cache.
Ok sure, so I hope below logic will keep this disabled:
if (crtc_state->has_psr2 && IS_TIGERLAKE(dev_priv))
cache->plane.visible = false;
if (!cache->plane.visible)
return;
Will update and re-send the patch.
Thanks & Regards,
Uma Shankar
> My plan is to eliminate most of the this params/cache mess and just cache the
> things fbc really needs for hw activate/deactivate. I do have a wip branch but
> haven't had time recently to continue the work.
>
> > + IS_TIGERLAKE(dev_priv)) {
> > + fbc->no_fbc_reason = "not supported with PSR2";
> > + return false;
> > + }
> > +
> > if (!intel_fbc_can_enable(dev_priv))
> > return false;
> >
> > --
> > 2.26.2
>
> --
> Ville Syrjälä
> Intel
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