On Thu, Nov 12, 2020 at 01:44:36PM +0200, Jani Nikula wrote:
> Let's try to not add new ones while we're phasing out I915_READ() and
> I915_WRITE().
>
> Fixes: 27a6bc802bd9 ("drm/i915/dg1: Initialize RAWCLK properly")
> Signed-off-by: Jani Nikula <jani.nikula@xxxxxxxxx>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index c449d28d0560..088d5908176c 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2710,8 +2710,8 @@ static int dg1_rawclk(struct drm_i915_private *dev_priv)
> * DG1 always uses a 38.4 MHz rawclk. The bspec tells us
> * "Program Numerator=2, Denominator=4, Divider=37 decimal."
> */
> - I915_WRITE(PCH_RAWCLK_FREQ,
> - CNP_RAWCLK_DEN(4) | CNP_RAWCLK_DIV(37) | ICP_RAWCLK_NUM(2));
> + intel_de_write(dev_priv, PCH_RAWCLK_FREQ,
> + CNP_RAWCLK_DEN(4) | CNP_RAWCLK_DIV(37) | ICP_RAWCLK_NUM(2));
>
> return 38400;
> }
> --
> 2.20.1
>
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