On Tue, Nov 10, 2020 at 01:12:39AM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> Move cnl_get_ddi_pll() into a better spot from between
> icl_get_ddi_pll() and dg1_get_ddi_pll(). Also reorder
> the calls to the skl and bxt functions because ocd.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Reviewed-by: Imre Deak <imre.deak@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 48 ++++++++++----------
> 1 file changed, 24 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 8ab622c0186e..322db0f3bbc6 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -11033,28 +11033,6 @@ static void dg1_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
> icl_set_active_port_dpll(pipe_config, port_dpll_id);
> }
>
> -static void cnl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
> - struct intel_crtc_state *pipe_config)
> -{
> - struct intel_shared_dpll *pll;
> - enum intel_dpll_id id;
> - bool pll_active;
> - u32 temp;
> -
> - temp = intel_de_read(dev_priv, DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
> - id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
> -
> - if (drm_WARN_ON(&dev_priv->drm, id < SKL_DPLL0 || id > SKL_DPLL2))
> - return;
> -
> - pll = intel_get_shared_dpll_by_id(dev_priv, id);
> -
> - pipe_config->shared_dpll = pll;
> - pll_active = intel_dpll_get_hw_state(dev_priv, pll,
> - &pipe_config->dpll_hw_state);
> - drm_WARN_ON(&dev_priv->drm, !pll_active);
> -}
> -
> static void icl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
> struct intel_crtc_state *pipe_config)
> {
> @@ -11109,6 +11087,28 @@ static void icl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
> icl_set_active_port_dpll(pipe_config, port_dpll_id);
> }
>
> +static void cnl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
> + struct intel_crtc_state *pipe_config)
> +{
> + struct intel_shared_dpll *pll;
> + enum intel_dpll_id id;
> + bool pll_active;
> + u32 temp;
> +
> + temp = intel_de_read(dev_priv, DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
> + id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
> +
> + if (drm_WARN_ON(&dev_priv->drm, id < SKL_DPLL0 || id > SKL_DPLL2))
> + return;
> +
> + pll = intel_get_shared_dpll_by_id(dev_priv, id);
> +
> + pipe_config->shared_dpll = pll;
> + pll_active = intel_dpll_get_hw_state(dev_priv, pll,
> + &pipe_config->dpll_hw_state);
> + drm_WARN_ON(&dev_priv->drm, !pll_active);
> +}
> +
> static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
> enum port port,
> struct intel_crtc_state *pipe_config)
> @@ -11382,10 +11382,10 @@ static void hsw_get_ddi_port_state(struct intel_crtc *crtc,
> icl_get_ddi_pll(dev_priv, port, pipe_config);
> else if (IS_CANNONLAKE(dev_priv))
> cnl_get_ddi_pll(dev_priv, port, pipe_config);
> - else if (IS_GEN9_BC(dev_priv))
> - skl_get_ddi_pll(dev_priv, port, pipe_config);
> else if (IS_GEN9_LP(dev_priv))
> bxt_get_ddi_pll(dev_priv, port, pipe_config);
> + else if (IS_GEN9_BC(dev_priv))
> + skl_get_ddi_pll(dev_priv, port, pipe_config);
> else
> hsw_get_ddi_pll(dev_priv, port, pipe_config);
>
> --
> 2.26.2
>
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