On Thu, 2020-11-05 at 01:26 +0530, Uma Shankar wrote:
> There are some corner cases wrt underrun when we enable
> FBC with PSR2 on TGL. Recommendation from hardware is to
> keep this combination disabled.
Do you have any references to this? HSD? BSpec?
>
> Signed-off-by: Uma Shankar <uma.shankar@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_fbc.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> index a5b072816a7b..32c411414908 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -799,6 +799,12 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc)
> struct intel_fbc *fbc = &dev_priv->fbc;
> struct intel_fbc_state_cache *cache = &fbc->state_cache;
>
>
>
>
> + if (dev_priv->psr.sink_psr2_support &&
> + IS_TIGERLAKE(dev_priv)) {
> + fbc->no_fbc_reason = "not supported with PSR2";
> + return false;
> + }
> +
> if (!intel_fbc_can_enable(dev_priv))
> return false;
>
>
>
>
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