Hi 2013/2/25 Rodrigo Vivi <rodrigo.vivi at gmail.com>: > According to HSW PM Programming guide it is not needed touch this registers > or setting these values anymore. > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi at gmail.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni at intel.com> > --- > drivers/gpu/drm/i915/intel_pm.c | 11 ++--------- > 1 file changed, 2 insertions(+), 9 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index fbe9779..322c562 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -2702,9 +2702,7 @@ static void hsw_enable_rps(struct drm_device *dev) > /* disable the counters and set deterministic thresholds */ > I915_WRITE(GEN6_RC_CONTROL, 0); > > - I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16); > - I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30); > - I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30); > + I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); > I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); > I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); > > @@ -2712,10 +2710,7 @@ static void hsw_enable_rps(struct drm_device *dev) > I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); > > I915_WRITE(GEN6_RC_SLEEP, 0); > - I915_WRITE(GEN6_RC1e_THRESHOLD, 1000); > I915_WRITE(GEN6_RC6_THRESHOLD, 50000); > - I915_WRITE(GEN6_RC6p_THRESHOLD, 100000); > - I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */ > > /* Check if we are enabling RC6 */ > rc6_mode = intel_enable_rc6(dev_priv->dev); > @@ -2731,9 +2726,7 @@ static void hsw_enable_rps(struct drm_device *dev) > GEN6_RC_CTL_HW_ENABLE); > > I915_WRITE(GEN6_RPNSWREQ, > - HSW_FREQUENCY(10) | > - GEN6_OFFSET(0) | > - GEN6_AGGRESSIVE_TURBO); > + HSW_FREQUENCY(10)); > I915_WRITE(GEN6_RC_VIDEO_FREQ, > HSW_FREQUENCY(12)); > > -- > 1.8.1.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Paulo Zanoni
