Hi 2013/2/25 Rodrigo Vivi <rodrigo.vivi at gmail.com>: > According to HSW PM programming guide, frequency bits starts at > 24 instead of 25 This looks incomplete. Please check all the cases where RPNSWREQ is used, I think we need to fix them too. Also, according to the PM programming guide, all the other RPNSWREQ bits are reserved/read-only, but I still see our code trying to set some of these bits (even if it's trying to set it to zero), so I guess that on Haswell all the writes to RPNSWREQ should only contain the HSW_FREQUENCY macro, not others. And for those other bits, we need to discover where did they go. > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi at gmail.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 1 + > drivers/gpu/drm/i915/intel_pm.c | 4 ++-- > 2 files changed, 3 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 527b664..ef47cee 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -4184,6 +4184,7 @@ > #define GEN6_RPNSWREQ 0xA008 > #define GEN6_TURBO_DISABLE (1<<31) > #define GEN6_FREQUENCY(x) ((x)<<25) > +#define HSW_FREQUENCY(x) ((x)<<24) > #define GEN6_OFFSET(x) ((x)<<19) > #define GEN6_AGGRESSIVE_TURBO (0<<15) > #define GEN6_RC_VIDEO_FREQ 0xA00C > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index e8656fd..fbe9779 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -2731,11 +2731,11 @@ static void hsw_enable_rps(struct drm_device *dev) > GEN6_RC_CTL_HW_ENABLE); > > I915_WRITE(GEN6_RPNSWREQ, > - GEN6_FREQUENCY(10) | > + HSW_FREQUENCY(10) | > GEN6_OFFSET(0) | > GEN6_AGGRESSIVE_TURBO); > I915_WRITE(GEN6_RC_VIDEO_FREQ, > - GEN6_FREQUENCY(12)); > + HSW_FREQUENCY(12)); > > I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); > I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, > -- > 1.8.1.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Paulo Zanoni
