Quoting Mika Kuoppala (2020-11-03 12:44:53) > Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> writes: > > > In a simple test case that writes to scratch and then busy-waits for the > > batch to be signaled, we observe that the signal is before the write is > > posted. That is bad news. > > > > Splitting the flush + write_dword into two separate flush_dw prevents > > the issue from being reproduced, we can presume the post-sync op is not > > so post-sync. > > > > Only thing that is mildly surpricing is that first one doesnt > need postop write. The MI_FLUSH_DW is stalling, so the second will^W should wait for the first to complete. (And we don't want to do the write from the first as we observe that write is too early.) -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
