As per W/A implemented for TGL to program half of the nominal
DCO divider fraction value which is also applicable on EHL.
Cc: Deak Imre <imre.deak@xxxxxxxxx>
Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@xxxxxxxxx>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 12 +++++++-----
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index eaef7a2d041f..0f3208d3c083 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -2636,13 +2636,15 @@ static bool cnl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
}
/*
- * Display WA #22010492432: tgl
+ * Display WA #22010492432: ehl, tgl
* Program half of the nominal DCO divider fraction value.
*/
static bool
-tgl_combo_pll_div_frac_wa_needed(struct drm_i915_private *i915)
+combo_pll_div_frac_wa_needed(struct drm_i915_private *i915)
{
- return IS_TIGERLAKE(i915) && i915->dpll.ref_clks.nssc == 38400;
+ return (IS_PLATFORM(i915, INTEL_ELKHARTLAKE) ||
+ IS_TIGERLAKE(i915)) &&
+ i915->dpll.ref_clks.nssc == 38400;
}
static int __cnl_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
@@ -2696,7 +2698,7 @@ static int __cnl_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
dco_fraction = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
DPLL_CFGCR0_DCO_FRACTION_SHIFT;
- if (tgl_combo_pll_div_frac_wa_needed(dev_priv))
+ if (combo_pll_div_frac_wa_needed(dev_priv))
dco_fraction *= 2;
dco_freq += (dco_fraction * ref_clock) / 0x8000;
@@ -3086,7 +3088,7 @@ static void icl_calc_dpll_state(struct drm_i915_private *i915,
memset(pll_state, 0, sizeof(*pll_state));
- if (tgl_combo_pll_div_frac_wa_needed(i915))
+ if (combo_pll_div_frac_wa_needed(i915))
dco_fraction = DIV_ROUND_CLOSEST(dco_fraction, 2);
pll_state->cfgcr0 = DPLL_CFGCR0_DCO_FRACTION(dco_fraction) |
--
2.28.0
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