From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Pass the crtc+cpu_transcoder rather than the crtc state to
intel_dsc_power_domain(). This should allow us to reuse it
during readout as well.
Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 3 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 3 +-
drivers/gpu/drm/i915/display/intel_vdsc.c | 54 +++++++++++------------
drivers/gpu/drm/i915/display/intel_vdsc.h | 6 ++-
4 files changed, 34 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 096652921453..462321ba5133 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1613,6 +1613,7 @@ static int gen11_dsi_compute_config(struct intel_encoder *encoder,
static void gen11_dsi_get_power_domains(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state)
{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
get_dsi_io_power_domains(i915,
@@ -1620,7 +1621,7 @@ static void gen11_dsi_get_power_domains(struct intel_encoder *encoder,
if (crtc_state->dsc.compression_enable)
intel_display_power_get(i915,
- intel_dsc_power_domain(crtc_state));
+ intel_dsc_power_domain(crtc, crtc_state->cpu_transcoder));
}
static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index bb0b9930958f..4407ddbca1ff 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2188,6 +2188,7 @@ intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port)
static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state)
{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_digital_port *dig_port;
enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
@@ -2222,7 +2223,7 @@ static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
*/
if (crtc_state->dsc.compression_enable)
intel_display_power_get(dev_priv,
- intel_dsc_power_domain(crtc_state));
+ intel_dsc_power_domain(crtc, crtc_state->cpu_transcoder));
}
void intel_ddi_enable_pipe_clock(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index c5735c365659..156e1689066b 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -357,11 +357,10 @@ bool intel_dsc_source_support(struct intel_encoder *encoder,
return false;
}
-static bool is_pipe_dsc(const struct intel_crtc_state *crtc_state)
+static bool is_pipe_dsc(struct intel_crtc *crtc,
+ enum transcoder cpu_transcoder)
{
- const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- const struct drm_i915_private *i915 = to_i915(crtc->base.dev);
- enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
if (INTEL_GEN(i915) >= 12)
return true;
@@ -465,9 +464,8 @@ int intel_dsc_compute_params(struct intel_encoder *encoder,
}
enum intel_display_power_domain
-intel_dsc_power_domain(const struct intel_crtc_state *crtc_state)
+intel_dsc_power_domain(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
@@ -484,7 +482,7 @@ intel_dsc_power_domain(const struct intel_crtc_state *crtc_state)
*/
if (INTEL_GEN(i915) >= 12 && !IS_ROCKETLAKE(i915) && pipe == PIPE_A)
return POWER_DOMAIN_TRANSCODER_VDSC_PW2;
- else if (is_pipe_dsc(crtc_state))
+ else if (is_pipe_dsc(crtc, cpu_transcoder))
return POWER_DOMAIN_PIPE(pipe);
else
return POWER_DOMAIN_TRANSCODER_VDSC_PW2;
@@ -517,7 +515,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder,
if (vdsc_cfg->vbr_enable)
pps_val |= DSC_VBR_ENABLE;
drm_info(&dev_priv->drm, "PPS0 = 0x%08x\n", pps_val);
- if (!is_pipe_dsc(crtc_state)) {
+ if (!is_pipe_dsc(crtc, crtc_state->cpu_transcoder)) {
intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_0,
pps_val);
/*
@@ -541,7 +539,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder,
pps_val = 0;
pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel);
drm_info(&dev_priv->drm, "PPS1 = 0x%08x\n", pps_val);
- if (!is_pipe_dsc(crtc_state)) {
+ if (!is_pipe_dsc(crtc, crtc_state->cpu_transcoder)) {
intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_1,
pps_val);
/*
@@ -566,7 +564,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder,
pps_val |= DSC_PIC_HEIGHT(vdsc_cfg->pic_height) |
DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances);
drm_info(&dev_priv->drm, "PPS2 = 0x%08x\n", pps_val);
- if (!is_pipe_dsc(crtc_state)) {
+ if (!is_pipe_dsc(crtc, crtc_state->cpu_transcoder)) {
intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_2,
pps_val);
/*
@@ -591,7 +589,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder,
pps_val |= DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) |
DSC_SLICE_WIDTH(vdsc_cfg->slice_width);
drm_info(&dev_priv->drm, "PPS3 = 0x%08x\n", pps_val);
- if (!is_pipe_dsc(crtc_state)) {
+ if (!is_pipe_dsc(crtc, crtc_state->cpu_transcoder)) {
intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_3,
pps_val);
/*
@@ -616,7 +614,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder,
pps_val |= DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) |
DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay);
drm_info(&dev_priv->drm, "PPS4 = 0x%08x\n", pps_val);
- if (!is_pipe_dsc(crtc_state)) {
+ if (!is_pipe_dsc(crtc, crtc_state->cpu_transcoder)) {
intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_4,
pps_val);
/*
@@ -641,7 +639,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder,
pps_val |= DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) |
DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval);
drm_info(&dev_priv->drm, "PPS5 = 0x%08x\n", pps_val);
- if (!is_pipe_dsc(crtc_state)) {
+ if (!is_pipe_dsc(crtc, crtc_state->cpu_transcoder)) {
intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_5,
pps_val);
/*
@@ -668,7 +666,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder,
DSC_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) |
DSC_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp);
drm_info(&dev_priv->drm, "PPS6 = 0x%08x\n", pps_val);
- if (!is_pipe_dsc(crtc_state)) {
+ if (!is_pipe_dsc(crtc, crtc_state->cpu_transcoder)) {
intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_6,
pps_val);
/*
@@ -693,7 +691,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder,
pps_val |= DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) |
DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset);
drm_info(&dev_priv->drm, "PPS7 = 0x%08x\n", pps_val);
- if (!is_pipe_dsc(crtc_state)) {
+ if (!is_pipe_dsc(crtc, crtc_state->cpu_transcoder)) {
intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_7,
pps_val);
/*
@@ -718,7 +716,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder,
pps_val |= DSC_FINAL_OFFSET(vdsc_cfg->final_offset) |
DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset);
drm_info(&dev_priv->drm, "PPS8 = 0x%08x\n", pps_val);
- if (!is_pipe_dsc(crtc_state)) {
+ if (!is_pipe_dsc(crtc, crtc_state->cpu_transcoder)) {
intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_8,
pps_val);
/*
@@ -743,7 +741,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder,
pps_val |= DSC_RC_MODEL_SIZE(DSC_RC_MODEL_SIZE_CONST) |
DSC_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST);
drm_info(&dev_priv->drm, "PPS9 = 0x%08x\n", pps_val);
- if (!is_pipe_dsc(crtc_state)) {
+ if (!is_pipe_dsc(crtc, crtc_state->cpu_transcoder)) {
intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_9,
pps_val);
/*
@@ -770,7 +768,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder,
DSC_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) |
DSC_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST);
drm_info(&dev_priv->drm, "PPS10 = 0x%08x\n", pps_val);
- if (!is_pipe_dsc(crtc_state)) {
+ if (!is_pipe_dsc(crtc, crtc_state->cpu_transcoder)) {
intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_10,
pps_val);
/*
@@ -798,7 +796,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder,
DSC_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height /
vdsc_cfg->slice_height);
drm_info(&dev_priv->drm, "PPS16 = 0x%08x\n", pps_val);
- if (!is_pipe_dsc(crtc_state)) {
+ if (!is_pipe_dsc(crtc, crtc_state->cpu_transcoder)) {
intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_16,
pps_val);
/*
@@ -827,7 +825,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder,
drm_info(&dev_priv->drm, " RC_BUF_THRESH%d = 0x%08x\n", i,
rc_buf_thresh_dword[i / 4]);
}
- if (!is_pipe_dsc(crtc_state)) {
+ if (!is_pipe_dsc(crtc, crtc_state->cpu_transcoder)) {
intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_0,
rc_buf_thresh_dword[0]);
intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_0_UDW,
@@ -884,7 +882,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder,
drm_info(&dev_priv->drm, " RC_RANGE_PARAM_%d = 0x%08x\n", i,
rc_range_params_dword[i / 2]);
}
- if (!is_pipe_dsc(crtc_state)) {
+ if (!is_pipe_dsc(crtc, crtc_state->cpu_transcoder)) {
intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_0,
rc_range_params_dword[0]);
intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_0_UDW,
@@ -987,13 +985,13 @@ void intel_dsc_get_config(struct intel_encoder *encoder,
if (!intel_dsc_source_support(encoder, crtc_state))
return;
- power_domain = intel_dsc_power_domain(crtc_state);
+ power_domain = intel_dsc_power_domain(crtc, crtc_state->cpu_transcoder);
wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
if (!wakeref)
return;
- if (!is_pipe_dsc(crtc_state)) {
+ if (!is_pipe_dsc(crtc, crtc_state->cpu_transcoder)) {
dss_ctl1 = intel_de_read(dev_priv, DSS_CTL1);
dss_ctl2 = intel_de_read(dev_priv, DSS_CTL2);
} else {
@@ -1011,7 +1009,7 @@ void intel_dsc_get_config(struct intel_encoder *encoder,
/* FIXME: add more state readout as needed */
/* PPS1 */
- if (!is_pipe_dsc(crtc_state))
+ if (!is_pipe_dsc(crtc, crtc_state->cpu_transcoder))
val = intel_de_read(dev_priv, DSCA_PICTURE_PARAMETER_SET_1);
else
val = intel_de_read(dev_priv,
@@ -1075,7 +1073,7 @@ void intel_dsc_enable(struct intel_encoder *encoder,
/* Enable Power wells for VDSC/joining */
intel_display_power_get(dev_priv,
- intel_dsc_power_domain(crtc_state));
+ intel_dsc_power_domain(crtc, crtc_state->cpu_transcoder));
intel_dsc_pps_configure(encoder, crtc_state);
@@ -1084,7 +1082,7 @@ void intel_dsc_enable(struct intel_encoder *encoder,
else
intel_dsc_dp_pps_write(encoder, crtc_state);
- if (!is_pipe_dsc(crtc_state)) {
+ if (!is_pipe_dsc(crtc, crtc_state->cpu_transcoder)) {
dss_ctl1_reg = DSS_CTL1;
dss_ctl2_reg = DSS_CTL2;
} else {
@@ -1111,7 +1109,7 @@ void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state)
if (!old_crtc_state->dsc.compression_enable)
return;
- if (!is_pipe_dsc(old_crtc_state)) {
+ if (!is_pipe_dsc(crtc, old_crtc_state->cpu_transcoder)) {
dss_ctl1_reg = DSS_CTL1;
dss_ctl2_reg = DSS_CTL2;
} else {
@@ -1132,5 +1130,5 @@ void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state)
/* Disable Power wells for VDSC/joining */
intel_display_power_put_unchecked(dev_priv,
- intel_dsc_power_domain(old_crtc_state));
+ intel_dsc_power_domain(crtc, old_crtc_state->cpu_transcoder));
}
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.h b/drivers/gpu/drm/i915/display/intel_vdsc.h
index e56a3254c214..acf1ce9c4a6e 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.h
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.h
@@ -8,8 +8,10 @@
#include <linux/types.h>
-struct intel_encoder;
+enum transcoder;
+struct intel_crtc;
struct intel_crtc_state;
+struct intel_encoder;
bool intel_dsc_source_support(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
@@ -21,6 +23,6 @@ int intel_dsc_compute_params(struct intel_encoder *encoder,
void intel_dsc_get_config(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state);
enum intel_display_power_domain
-intel_dsc_power_domain(const struct intel_crtc_state *crtc_state);
+intel_dsc_power_domain(struct intel_crtc *crtc, enum transcoder cpu_transcoder);
#endif /* __INTEL_VDSC_H__ */
--
2.26.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
