On Fri, Oct 16, 2020 at 01:18:37PM -0700, José Roberto de Souza wrote:
> This sequence is not part of "Sequences to Initialize Display" but
> as noted in the MBus page the DBUF_CTL.Tracker_state_service needs
> to be set to 8.
>
> BSpec: 49213
> Signed-off-by: José Roberto de Souza <jose.souza@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_display_power.c | 13 +++++++++++++
> drivers/gpu/drm/i915/i915_reg.h | 14 +++++++++-----
> 2 files changed, 22 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 45806cfc679a..db36ab02e7d7 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -4771,6 +4771,17 @@ static void gen9_dbuf_disable(struct drm_i915_private *dev_priv)
> gen9_dbuf_slices_update(dev_priv, 0);
> }
>
> +static void gen12_dbuf_slices_config(struct drm_i915_private *dev_priv)
> +{
> + const int num_slices = INTEL_INFO(dev_priv)->num_supported_dbuf_slices;
> + enum dbuf_slice slice;
> +
> + for (slice = DBUF_S1; slice < num_slices; slice++)
Minor nitpick; if we're starting from symbolic value DBUF_S1, we should
probably end at 'DBUF_S1 + num_slices' for consistency.
> + intel_de_rmw(dev_priv, DBUF_CTL_S(slice),
> + DBUF_TRACKER_STATE_SERVICE_MASK,
> + DBUF_TRACKER_STATE_SERVICE(8));
> +}
> +
> static void icl_mbus_init(struct drm_i915_private *dev_priv)
> {
> unsigned long abox_regs = INTEL_INFO(dev_priv)->abox_mask;
> @@ -5340,6 +5351,8 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
> /* 4. Enable CDCLK. */
> intel_cdclk_init_hw(dev_priv);
>
> + if (INTEL_GEN(dev_priv) >= 12)
> + gen12_dbuf_slices_config(dev_priv);
> /* 5. Enable DBUF. */
Minor nitpick: should there be a blank between these additions and the
comment?
Aside from those two minor things,
Reviewed-by: Matt Roper <matthew.d.roper@xxxxxxxxx>
> gen9_dbuf_enable(dev_priv);
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 6d97e6286c2d..c38901e2f81c 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7927,11 +7927,15 @@ enum {
> #define DISP_ARB_CTL2 _MMIO(0x45004)
> #define DISP_DATA_PARTITION_5_6 (1 << 6)
> #define DISP_IPC_ENABLE (1 << 3)
> -#define _DBUF_CTL_S1 0x45008
> -#define _DBUF_CTL_S2 0x44FE8
> -#define DBUF_CTL_S(slice) _MMIO(_PICK_EVEN(slice, _DBUF_CTL_S1, _DBUF_CTL_S2))
> -#define DBUF_POWER_REQUEST (1 << 31)
> -#define DBUF_POWER_STATE (1 << 30)
> +
> +#define _DBUF_CTL_S1 0x45008
> +#define _DBUF_CTL_S2 0x44FE8
> +#define DBUF_CTL_S(slice) _MMIO(_PICK_EVEN(slice, _DBUF_CTL_S1, _DBUF_CTL_S2))
> +#define DBUF_POWER_REQUEST REG_BIT(31)
> +#define DBUF_POWER_STATE REG_BIT(30)
> +#define DBUF_TRACKER_STATE_SERVICE_MASK REG_GENMASK(23, 19)
> +#define DBUF_TRACKER_STATE_SERVICE(x) REG_FIELD_PREP(DBUF_TRACKER_STATE_SERVICE_MASK, x)
> +
> #define GEN7_MSG_CTL _MMIO(0x45010)
> #define WAIT_FOR_PCH_RESET_ACK (1 << 1)
> #define WAIT_FOR_PCH_FLR_ACK (1 << 0)
> --
> 2.28.0
>
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--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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