From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> Use hpd_pin to parametrize BXT_DE_PORT_HP_DDI() to make it clear these have nothing to do with DDI ports or PHYs as such. The only thing that matters is the HPD pin assignment. Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> --- drivers/gpu/drm/i915/i915_irq.c | 12 ++++++------ drivers/gpu/drm/i915/i915_reg.h | 12 ++++++------ 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index d9438194c2f0..9b92b95f7a6f 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -126,9 +126,9 @@ static const u32 hpd_status_i915[HPD_NUM_PINS] = { }; static const u32 hpd_bxt[HPD_NUM_PINS] = { - [HPD_PORT_A] = BXT_DE_PORT_HP_DDIA, - [HPD_PORT_B] = BXT_DE_PORT_HP_DDIB, - [HPD_PORT_C] = BXT_DE_PORT_HP_DDIC, + [HPD_PORT_A] = BXT_DE_PORT_HP_DDI(HPD_PORT_A), + [HPD_PORT_B] = BXT_DE_PORT_HP_DDI(HPD_PORT_B), + [HPD_PORT_C] = BXT_DE_PORT_HP_DDI(HPD_PORT_C), }; static const u32 hpd_gen11[HPD_NUM_PINS] = { @@ -3391,13 +3391,13 @@ static void __bxt_hpd_detection_setup(struct drm_i915_private *dev_priv, * For BXT invert bit has to be set based on AOB design * for HPD detection logic, update it based on VBT fields. */ - if ((enabled_irqs & BXT_DE_PORT_HP_DDIA) && + if ((enabled_irqs & BXT_DE_PORT_HP_DDI(HPD_PORT_A)) && intel_bios_is_port_hpd_inverted(dev_priv, PORT_A)) hotplug |= BXT_DDIA_HPD_INVERT; - if ((enabled_irqs & BXT_DE_PORT_HP_DDIB) && + if ((enabled_irqs & BXT_DE_PORT_HP_DDI(HPD_PORT_B)) && intel_bios_is_port_hpd_inverted(dev_priv, PORT_B)) hotplug |= BXT_DDIB_HPD_INVERT; - if ((enabled_irqs & BXT_DE_PORT_HP_DDIC) && + if ((enabled_irqs & BXT_DE_PORT_HP_DDI(HPD_PORT_C)) && intel_bios_is_port_hpd_inverted(dev_priv, PORT_C)) hotplug |= BXT_DDIC_HPD_INVERT; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 2e378d9b21c5..72f93ec38aea 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7786,6 +7786,8 @@ enum { (GEN9_DE_PIPE_IRQ_FAULT_ERRORS | \ GEN11_PIPE_PLANE5_FAULT) +#define _HPD_PIN_DDI(hpd_pin) ((hpd_pin) - HPD_PORT_A) + #define GEN8_DE_PORT_ISR _MMIO(0x44440) #define GEN8_DE_PORT_IMR _MMIO(0x44444) #define GEN8_DE_PORT_IIR _MMIO(0x44448) @@ -7799,12 +7801,10 @@ enum { #define GEN9_AUX_CHANNEL_B (1 << 25) #define DSI1_TE (1 << 24) #define DSI0_TE (1 << 23) -#define BXT_DE_PORT_HP_DDIC (1 << 5) -#define BXT_DE_PORT_HP_DDIB (1 << 4) -#define BXT_DE_PORT_HP_DDIA (1 << 3) -#define BXT_DE_PORT_HOTPLUG_MASK (BXT_DE_PORT_HP_DDIA | \ - BXT_DE_PORT_HP_DDIB | \ - BXT_DE_PORT_HP_DDIC) +#define BXT_DE_PORT_HP_DDI(hpd_pin) REG_BIT(3 + _HPD_PIN_DDI(hpd_pin)) +#define BXT_DE_PORT_HOTPLUG_MASK (BXT_DE_PORT_HP_DDI(HPD_PORT_A) | \ + BXT_DE_PORT_HP_DDI(HPD_PORT_B) | \ + BXT_DE_PORT_HP_DDI(HPD_PORT_C)) #define GEN8_PORT_DP_A_HOTPLUG (1 << 3) #define BXT_DE_PORT_GMBUS (1 << 1) #define GEN8_AUX_CHANNEL_A (1 << 0) -- 2.26.2 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx