Add the MISSING_CASE() for the p0, p2 decoding during WRPLL HW readout
and move the corresponding check for p1 next to where it's read out.
Signed-off-by: Imre Deak <imre.deak@xxxxxxxxx>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 11 ++++++++---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 2cc0e84e41ea..27a8c281382c 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -2662,6 +2662,8 @@ static int __cnl_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
else
p1 = 1;
+ if (drm_WARN_ON(&dev_priv->drm, p1 == 0))
+ return 0;
switch (p0) {
case DPLL_CFGCR1_PDIV_2:
@@ -2676,6 +2678,9 @@ static int __cnl_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
case DPLL_CFGCR1_PDIV_7:
p0 = 7;
break;
+ default:
+ MISSING_CASE(p0);
+ return 0;
}
switch (p2) {
@@ -2688,6 +2693,9 @@ static int __cnl_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
case DPLL_CFGCR1_KDIV_3:
p2 = 3;
break;
+ default:
+ MISSING_CASE(p2);
+ return 0;
}
dco_freq = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) *
@@ -2701,9 +2709,6 @@ static int __cnl_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
dco_freq += (dco_fraction * ref_clock) / 0x8000;
- if (drm_WARN_ON(&dev_priv->drm, p0 == 0 || p1 == 0 || p2 == 0))
- return 0;
-
return dco_freq / (p0 * p1 * p2 * 5);
}
--
2.25.1
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