On Mon, Oct 05, 2020 at 09:36:35PM +0000, Shankar, Uma wrote:
>
>
> > -----Original Message-----
> > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> > Sent: Tuesday, September 29, 2020 9:51 PM
> > To: Shankar, Uma <uma.shankar@xxxxxxxxx>
> > Cc: intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> > Subject: Re: [v6 06/11] drm/i915/display: Implement infoframes readback for
> > LSPCON
> >
> > On Tue, Sep 15, 2020 at 02:30:42AM +0530, Uma Shankar wrote:
> > > Implemented Infoframes enabled readback for LSPCON devices.
> > > This will help align the implementation with state readback
> > > infrastructure.
> > >
> > > v2: Added proper bitmask of enabled infoframes as per Ville's
> > > recommendation.
> > >
> > > Signed-off-by: Uma Shankar <uma.shankar@xxxxxxxxx>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_lspcon.c | 57
> > > ++++++++++++++++++++-
> > > 1 file changed, 55 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c
> > > b/drivers/gpu/drm/i915/display/intel_lspcon.c
> > > index 60863b825cc5..565913b8e656 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_lspcon.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
> > > @@ -576,11 +576,64 @@ void lspcon_set_infoframes(struct intel_encoder
> > *encoder,
> > > buf, ret);
> > > }
> > >
> > > +static bool _lspcon_read_avi_infoframe_enabled_mca(struct drm_dp_aux
> > > +*aux) {
> > > + int ret;
> > > + u32 val = 0;
> > > + u16 reg = LSPCON_MCA_AVI_IF_CTRL;
> > > +
> > > + ret = drm_dp_dpcd_read(aux, reg, &val, 1);
> > > + if (ret < 0) {
> > > + DRM_ERROR("DPCD read failed, address 0x%x\n", reg);
> > > + return false;
> > > + }
> > > +
> > > + return val & LSPCON_MCA_AVI_IF_KICKOFF; }
> > > +
> > > +static bool _lspcon_read_avi_infoframe_enabled_parade(struct
> > > +drm_dp_aux *aux) {
> > > + int ret;
> > > + u32 val = 0;
> > > + u16 reg = LSPCON_PARADE_AVI_IF_CTRL;
> > > +
> > > + ret = drm_dp_dpcd_read(aux, reg, &val, 1);
> > > + if (ret < 0) {
> > > + DRM_ERROR("DPCD read failed, address 0x%x\n", reg);
> > > + return false;
> > > + }
> > > +
> > > + return val & LSPCON_PARADE_AVI_IF_KICKOFF; }
> > > +
> > > u32 lspcon_infoframes_enabled(struct intel_encoder *encoder,
> > > const struct intel_crtc_state *pipe_config) {
> > > - /* FIXME actually read this from the hw */
> > > - return 0;
> > > + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > > + struct intel_lspcon *lspcon = enc_to_intel_lspcon(encoder);
> > > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > > + bool infoframes_enabled;
> > > + u32 val = 0;
> > > + u32 mask, tmp;
> > > +
> > > + if (lspcon->vendor == LSPCON_VENDOR_MCA)
> > > + infoframes_enabled =
> > _lspcon_read_avi_infoframe_enabled_mca(&intel_dp->aux);
> > > + else
> > > + infoframes_enabled =
> > > +_lspcon_read_avi_infoframe_enabled_parade(&intel_dp->aux);
> > > +
> > > + if (infoframes_enabled)
> > > + val |= VIDEO_DIP_ENABLE_AVI_HSW;
> >
> > Still not a fan of abusing the HSW specific reg values here.
>
> I just kept it so that rest of the infrastructure can be re-used easily. So the AVI and GMP
> bit fields will get re-used and will not require any separate handling.
Using the abstract infoframe types wouldn't prevent that.
>
> > > +
> > > + if (lspcon->hdr_supported) {
> > > + tmp = intel_de_read(dev_priv,
> > > + HSW_TVIDEO_DIP_CTL(pipe_config-
> > >cpu_transcoder));
> > > + mask = VIDEO_DIP_ENABLE_GMP_HSW;
> > > +
> > > + if (tmp & mask)
> > > + val |= mask;
> > > + }
> > > +
> > > + return val;
> > > }
> > >
> > > void lspcon_resume(struct intel_lspcon *lspcon)
> > > --
> > > 2.26.2
> >
> > --
> > Ville Syrjälä
> > Intel
--
Ville Syrjälä
Intel
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