On Tue, Oct 06, 2020 at 04:35:55AM +0300, Imre Deak wrote:
> The BIOS of at least one ASUS-Z170M system with an SKL I have programs
> the 101b WRPLL PDIV divider value, which is the encoding for PDIV=7 with
> bit#0 incorrectly set.
>
> This happens with the
>
> "3840x2160": 30 262750 3840 3888 3920 4000 2160 2163 2168 2191 0x48 0x9
>
> HDMI mode (scaled from a 1024x768 src fb) set by BIOS and the
>
> ref_clock=24000, dco_integer=383, dco_fraction=5802, pdiv=7, qdiv=1, kdiv=1
>
> WRPLL parameters (assuming PDIV=7 was the intended setting). This
> corresponds to 262749 PLL frequency/port clock.
>
> Later the driver sets the same mode for which it calculates the same
> dco_int/dco_frac/div WRPLL parameters (with the correct PDIV=7 encoding).
>
> Based on the above, let's assume that PDIV=7 was intended and the HW
> just ignores bit#0 in the PDIV register field for this setting, treating
> 100b and 101b encodings the same way.
>
> While at it add the MISSING_CASE() for the p0,p2 divider decodings.
>
> v2: (Ville)
> - Add a define for the incorrect divider value.
> - Emit only a debug message when detecting the incorrect divider value.
> - Use fallthrough from the incorrect divider value case.
> - Add the MISSING_CASE()s.
>
> v3: Return 0 freq for incorrect divider values. (Ville)
>
> Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> Signed-off-by: Imre Deak <imre.deak@xxxxxxxxx>
Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 13 +++++++++++++
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 2 files changed, 14 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index e08684e34078..fff4e154b391 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -1602,9 +1602,19 @@ static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915,
> case DPLL_CFGCR2_PDIV_3:
> p0 = 3;
> break;
> + case DPLL_CFGCR2_PDIV_7_INVALID:
> + /*
> + * Incorrect ASUS-Z170M BIOS setting, the HW seems to ignore bit#0,
> + * handling it the same way as PDIV_7.
> + */
> + drm_dbg_kms(&i915->drm, "Invalid WRPLL PDIV divider value, fixing it.\n");
> + fallthrough;
> case DPLL_CFGCR2_PDIV_7:
> p0 = 7;
> break;
> + default:
> + MISSING_CASE(p0);
> + return 0;
> }
>
> switch (p2) {
> @@ -1620,6 +1630,9 @@ static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915,
> case DPLL_CFGCR2_KDIV_1:
> p2 = 1;
> break;
> + default:
> + MISSING_CASE(p2);
> + return 0;
> }
>
> dco_freq = (pll_state->cfgcr1 & DPLL_CFGCR1_DCO_INTEGER_MASK) *
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 88c215cf97d4..d911583526db 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -10261,6 +10261,7 @@ enum skl_power_gate {
> #define DPLL_CFGCR2_PDIV_2 (1 << 2)
> #define DPLL_CFGCR2_PDIV_3 (2 << 2)
> #define DPLL_CFGCR2_PDIV_7 (4 << 2)
> +#define DPLL_CFGCR2_PDIV_7_INVALID (5 << 2)
> #define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3)
>
> #define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1)
> --
> 2.25.1
--
Ville Syrjälä
Intel
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