✓ Fi.CI.BAT: success for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev7)

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Title: Project List - Patchwork
Patch Details
Series:drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev7)
URL:https://patchwork.freedesktop.org/series/82173/
State:success
Details:https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18630/index.html

CI Bug Log - changes from CI_DRM_9100 -> Patchwork_18630

Summary

SUCCESS

No regressions found.

External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18630/index.html

Known issues

Here are the changes found in Patchwork_18630 that come from known issues:

IGT changes

Issues hit

Possible fixes

Warnings

{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).

Participating hosts (44 -> 38)

Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus

Build changes

CI-20190529: 20190529
CI_DRM_9100: 62e000a556587d80f5c23b863195a30c073c7741 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5800: 982ca4122fd4f04ad3dfa80c6246f190b36e0c72 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18630: c9218b4e5fb4b047c75911a798897ab663fe158f @ git://anongit.freedesktop.org/gfx-ci/linux

== Linux commits ==

c9218b4e5fb4 drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock
c2ee2fe22455 drm/i915: Add an encoder hook to sanitize its state during init/resume
cf94f1fd7110 drm/i915: Check for unsupported DP link rates during initial commit
76cfbbbf6aa9 drm/i915: Move the initial fastset commit check to encoder hooks
479da4d9f49e drm/i915/skl: Work around incorrect BIOS WRPLL PDIV programming

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